@@ -112,6 +112,30 @@
};
};
+ L2_CA15: cache-controller@0 {
+ compatible = "cache";
+
+ arm,data-latency = <4 4 1>;
+ arm,tag-latency = <3 3 3>;
+ cache-unified;
+ cache-level = <2>;
+ cache-size = <0x200000>;
+ cache-sets = <4096>;
+ cache-block-size = <32>;
+ cache-line-size = <32>;
+ };
+
+ L2_CA7: cache-controller@1 {
+ compatible = "cache";
+
+ cache-unified;
+ cache-level = <2>;
+ cache-size = <0x80000>;
+ cache-sets = <2048>;
+ cache-block-size = <32>;
+ cache-line-size = <32>;
+ };
+
gic: interrupt-controller@f1001000 {
compatible = "arm,cortex-a15-gic";
#interrupt-cells = <3>;
Add device nodes for the L2 caches: - The L2 cache for the Cortex-A15 CPU cores is 2 MiB large (organized as 128 KiB x 16 ways), and requires the following settings: - Tag RAM latency: 3 cycles, - Data RAM latency: 4 cycles, - Data RAM setup: 1 cycle, - The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as 64 KiB x 8 ways). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> --- What are the DT bindings for a Cortex-A15 L2 cache controller? --- arch/arm/boot/dts/r8a7790.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)