From patchwork Thu Jun 4 18:53:29 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 6549331 X-Patchwork-Delegate: horms@verge.net.au Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id DF989C0020 for ; Thu, 4 Jun 2015 18:55:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1FFC8207B2 for ; Thu, 4 Jun 2015 18:55:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3D9EA206FE for ; Thu, 4 Jun 2015 18:55:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754210AbbFDSzT (ORCPT ); Thu, 4 Jun 2015 14:55:19 -0400 Received: from andre.telenet-ops.be ([195.130.132.53]:40505 "EHLO andre.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753973AbbFDSxr (ORCPT ); Thu, 4 Jun 2015 14:53:47 -0400 Received: from ayla.of.borg ([84.193.93.87]) by andre.telenet-ops.be with bizsmtp id cJtd1q00S1t5w8s01Jtduh; Thu, 04 Jun 2015 20:53:45 +0200 Received: from ramsan.of.borg ([192.168.97.29] helo=ramsan) by ayla.of.borg with esmtp (Exim 4.82) (envelope-from ) id 1Z0aGn-0006Jf-BX; Thu, 04 Jun 2015 20:53:37 +0200 Received: from geert by ramsan with local (Exim 4.82) (envelope-from ) id 1Z0aGv-0005nG-I5; Thu, 04 Jun 2015 20:53:45 +0200 From: Geert Uytterhoeven To: Simon Horman , Magnus Damm , "Rafael J. Wysocki" , Kevin Hilman , Ulf Hansson , Lina Iyer , Mark Rutland , Pawel Moll Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-sh@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH/RFC 03/15] ARM: shmobile: r8a7790 dtsi: Add L2 cache-controller nodes Date: Thu, 4 Jun 2015 20:53:29 +0200 Message-Id: <1433444021-22167-4-git-send-email-geert+renesas@glider.be> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1433444021-22167-1-git-send-email-geert+renesas@glider.be> References: <1433444021-22167-1-git-send-email-geert+renesas@glider.be> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add device nodes for the L2 caches: - The L2 cache for the Cortex-A15 CPU cores is 2 MiB large (organized as 128 KiB x 16 ways), and requires the following settings: - Tag RAM latency: 3 cycles, - Data RAM latency: 4 cycles, - Data RAM setup: 1 cycle, - The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as 64 KiB x 8 ways). Signed-off-by: Geert Uytterhoeven --- What are the DT bindings for a Cortex-A15 L2 cache controller? --- arch/arm/boot/dts/r8a7790.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 7fbcad087ee384e8..729172090f865e4d 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -112,6 +112,30 @@ }; }; + L2_CA15: cache-controller@0 { + compatible = "cache"; + + arm,data-latency = <4 4 1>; + arm,tag-latency = <3 3 3>; + cache-unified; + cache-level = <2>; + cache-size = <0x200000>; + cache-sets = <4096>; + cache-block-size = <32>; + cache-line-size = <32>; + }; + + L2_CA7: cache-controller@1 { + compatible = "cache"; + + cache-unified; + cache-level = <2>; + cache-size = <0x80000>; + cache-sets = <2048>; + cache-block-size = <32>; + cache-line-size = <32>; + }; + gic: interrupt-controller@f1001000 { compatible = "arm,cortex-a15-gic"; #interrupt-cells = <3>;