From patchwork Fri Jun 26 15:23:59 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Hutchings X-Patchwork-Id: 6682191 X-Patchwork-Delegate: horms@verge.net.au Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 7988EC05AC for ; Fri, 26 Jun 2015 15:24:09 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5B96520502 for ; Fri, 26 Jun 2015 15:24:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6CE2A204D9 for ; Fri, 26 Jun 2015 15:24:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753189AbbFZPYG (ORCPT ); Fri, 26 Jun 2015 11:24:06 -0400 Received: from ducie-dc1.codethink.co.uk ([185.25.241.215]:39356 "EHLO ducie-dc1.codethink.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752309AbbFZPYF (ORCPT ); Fri, 26 Jun 2015 11:24:05 -0400 Received: from localhost (localhost [127.0.0.1]) by ducie-dc1.codethink.co.uk (Postfix) with ESMTP id 5766E461911; Fri, 26 Jun 2015 16:24:04 +0100 (BST) X-Virus-Scanned: Debian amavisd-new at ducie-dc1.codethink.co.uk Received: from ducie-dc1.codethink.co.uk ([127.0.0.1]) by localhost (ducie-dc1.codethink.co.uk [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id IeSJTJQLjffn; Fri, 26 Jun 2015 16:24:00 +0100 (BST) Received: from xylophone (unknown [192.168.25.61]) by ducie-dc1.codethink.co.uk (Postfix) with ESMTPSA id 22CE54608AD; Fri, 26 Jun 2015 16:24:00 +0100 (BST) Message-ID: <1435332239.23818.13.camel@codethink.co.uk> Subject: [PATCH v3 6/6] ARM: shmobile: lager: Enable UHS-I SDR-50 From: Ben Hutchings To: Ian Molton , Laurent Pinchart Cc: linux-mmc@vger.kernel.org, linux-sh@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@lists.codethink.co.uk, Sergei Shtylyov , Simon Horman , Kuninori Morimoto Date: Fri, 26 Jun 2015 16:23:59 +0100 In-Reply-To: <1435332116.23818.7.camel@codethink.co.uk> References: <1435332116.23818.7.camel@codethink.co.uk> Organization: Codethink Ltd. X-Mailer: Evolution 3.12.9-1+b1 Mime-Version: 1.0 Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the "1v8" pinctrl state and sd-uhs-sdr50 property to SDHI{0,2}. Signed-off-by: Ben Hutchings --- arch/arm/boot/dts/r8a7790-lager.dts | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 5f68e53c58ae..c7db213054f6 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -312,11 +312,25 @@ sdhi0_pins: sd0 { renesas,groups = "sdhi0_data4", "sdhi0_ctrl"; renesas,function = "sdhi0"; + power-source = <0>; + }; + + sdhi0_pins_1v8: sd0_1v8 { + renesas,groups = "sdhi0_data4", "sdhi0_ctrl"; + renesas,function = "sdhi0"; + power-source = <1>; }; sdhi2_pins: sd2 { renesas,groups = "sdhi2_data4", "sdhi2_ctrl"; renesas,function = "sdhi2"; + power-source = <0>; + }; + + sdhi2_pins_1v8: sd2_1v8 { + renesas,groups = "sdhi2_data4", "sdhi2_ctrl"; + renesas,function = "sdhi2"; + power-source = <1>; }; mmc1_pins: mmc1 { @@ -486,7 +500,8 @@ &sdhi0 { pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; + pinctrl-1 = <&sdhi0_pins_1v8>; + pinctrl-names = "default", "1v8"; assigned-clocks = <&mstp3_clks R8A7790_CLK_SDHI0>; assigned-clock-rates = <156000000>; @@ -494,12 +509,14 @@ vmmc-supply = <&vcc_sdhi0>; vqmmc-supply = <&vccq_sdhi0>; cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; + sd-uhs-sdr50; status = "okay"; }; &sdhi2 { pinctrl-0 = <&sdhi2_pins>; - pinctrl-names = "default"; + pinctrl-1 = <&sdhi2_pins_1v8>; + pinctrl-names = "default", "1v8"; assigned-clocks = <&mstp3_clks R8A7790_CLK_SDHI2>; assigned-clock-rates = <97500000>; @@ -507,6 +524,7 @@ vmmc-supply = <&vcc_sdhi2>; vqmmc-supply = <&vccq_sdhi2>; cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; + sd-uhs-sdr50; status = "okay"; };