From patchwork Wed Jul 1 15:58:02 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 6704771 X-Patchwork-Delegate: horms@verge.net.au Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 8FFDC9F2F0 for ; Wed, 1 Jul 2015 16:00:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 81CD62077E for ; Wed, 1 Jul 2015 16:00:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 825B620779 for ; Wed, 1 Jul 2015 16:00:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754678AbbGAQA0 (ORCPT ); Wed, 1 Jul 2015 12:00:26 -0400 Received: from michel.telenet-ops.be ([195.130.137.88]:53241 "EHLO michel.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754641AbbGAP61 (ORCPT ); Wed, 1 Jul 2015 11:58:27 -0400 Received: from ayla.of.borg ([84.193.93.87]) by michel.telenet-ops.be with bizsmtp id n3yH1q00Y1t5w8s063yHU4; Wed, 01 Jul 2015 17:58:24 +0200 Received: from ramsan.of.borg ([192.168.97.29] helo=ramsan) by ayla.of.borg with esmtp (Exim 4.82) (envelope-from ) id 1ZAKOv-0006wU-EK; Wed, 01 Jul 2015 17:58:17 +0200 Received: from geert by ramsan with local (Exim 4.82) (envelope-from ) id 1ZAKP0-0000ph-5E; Wed, 01 Jul 2015 17:58:22 +0200 From: Geert Uytterhoeven To: Simon Horman , Magnus Damm , Michael Turquette , Stephen Boyd , Laurent Pinchart , "Rafael J. Wysocki" , Kevin Hilman , Ulf Hansson Cc: linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-sh@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v3 08/16] ARM: shmobile: r8a7779 dtsi: Add CPG/MSTP Clock Domain Date: Wed, 1 Jul 2015 17:58:02 +0200 Message-Id: <1435766290-3005-9-git-send-email-geert+renesas@glider.be> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1435766290-3005-1-git-send-email-geert+renesas@glider.be> References: <1435766290-3005-1-git-send-email-geert+renesas@glider.be> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add an appropriate "#power-domain-cells" property to the cpg_clocks device node, to create the CPG/MSTP Clock Domain. Add "power-domains" properties to all device nodes for devices that are part of the CPG/MSTP Clock Domain and can be power-managed through an MSTP clock. This applies to most on-SoC devices, which have a one-to-one mapping from SoC device to DT device node. Signed-off-by: Geert Uytterhoeven --- v3: - Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain", v2: - New. --- arch/arm/boot/dts/r8a7779.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index a2b5430d32575f99..6afa909865b52b71 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -173,6 +173,7 @@ reg = <0xffc70000 0x1000>; interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7779_CLK_I2C0>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -183,6 +184,7 @@ reg = <0xffc71000 0x1000>; interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7779_CLK_I2C1>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -193,6 +195,7 @@ reg = <0xffc72000 0x1000>; interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7779_CLK_I2C2>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -203,6 +206,7 @@ reg = <0xffc73000 0x1000>; interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7779_CLK_I2C3>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -212,6 +216,7 @@ interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7779_CLK_SCIF0>; clock-names = "sci_ick"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -221,6 +226,7 @@ interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7779_CLK_SCIF1>; clock-names = "sci_ick"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -230,6 +236,7 @@ interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7779_CLK_SCIF2>; clock-names = "sci_ick"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -239,6 +246,7 @@ interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7779_CLK_SCIF3>; clock-names = "sci_ick"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -248,6 +256,7 @@ interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7779_CLK_SCIF4>; clock-names = "sci_ick"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -257,6 +266,7 @@ interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7779_CLK_SCIF5>; clock-names = "sci_ick"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -278,6 +288,7 @@ <0 34 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7779_CLK_TMU0>; clock-names = "fck"; + power-domains = <&cpg_clocks>; #renesas,channels = <3>; @@ -292,6 +303,7 @@ <0 38 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7779_CLK_TMU1>; clock-names = "fck"; + power-domains = <&cpg_clocks>; #renesas,channels = <3>; @@ -306,6 +318,7 @@ <0 42 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7779_CLK_TMU2>; clock-names = "fck"; + power-domains = <&cpg_clocks>; #renesas,channels = <3>; @@ -317,6 +330,7 @@ reg = <0xfc600000 0x2000>; interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp1_clks R8A7779_CLK_SATA>; + power-domains = <&cpg_clocks>; }; sdhi0: sd@ffe4c000 { @@ -324,6 +338,7 @@ reg = <0xffe4c000 0x100>; interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7779_CLK_SDHI0>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -332,6 +347,7 @@ reg = <0xffe4d000 0x100>; interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7779_CLK_SDHI1>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -340,6 +356,7 @@ reg = <0xffe4e000 0x100>; interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7779_CLK_SDHI2>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -348,6 +365,7 @@ reg = <0xffe4f000 0x100>; interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7779_CLK_SDHI3>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -358,6 +376,7 @@ #address-cells = <1>; #size-cells = <0>; clocks = <&mstp0_clks R8A7779_CLK_HSPI>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -368,6 +387,7 @@ #address-cells = <1>; #size-cells = <0>; clocks = <&mstp0_clks R8A7779_CLK_HSPI>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -378,6 +398,7 @@ #address-cells = <1>; #size-cells = <0>; clocks = <&mstp0_clks R8A7779_CLK_HSPI>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -386,6 +407,7 @@ reg = <0 0xfff80000 0 0x40000>; interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp1_clks R8A7779_CLK_DU>; + power-domains = <&cpg_clocks>; status = "disabled"; ports { @@ -427,6 +449,7 @@ #clock-cells = <1>; clock-output-names = "plla", "z", "zs", "s", "s1", "p", "b", "out"; + #power-domain-cells = <0>; }; /* Fixed factor clocks */