From patchwork Thu Aug 27 19:02:31 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 7086771 X-Patchwork-Delegate: horms@verge.net.au Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 1D05EBEEC1 for ; Thu, 27 Aug 2015 19:02:41 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1E0FF20691 for ; Thu, 27 Aug 2015 19:02:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 25D0A208F6 for ; Thu, 27 Aug 2015 19:02:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752762AbbH0TCg (ORCPT ); Thu, 27 Aug 2015 15:02:36 -0400 Received: from baptiste.telenet-ops.be ([195.130.132.51]:51961 "EHLO baptiste.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751921AbbH0TCf (ORCPT ); Thu, 27 Aug 2015 15:02:35 -0400 Received: from ayla.of.borg ([31.5.182.137]) by baptiste.telenet-ops.be with bizsmtp id 9v2Z1r00E2yGKqv01v2Zrq; Thu, 27 Aug 2015 21:02:34 +0200 Received: from ramsan.of.borg ([192.168.97.29] helo=ramsan) by ayla.of.borg with esmtp (Exim 4.82) (envelope-from ) id 1ZV2RV-0000Of-5x; Thu, 27 Aug 2015 21:02:33 +0200 Received: from geert by ramsan with local (Exim 4.82) (envelope-from ) id 1ZV2RX-0000Nk-Og; Thu, 27 Aug 2015 21:02:35 +0200 From: Geert Uytterhoeven To: Kuninori Morimoto , Simon Horman , Magnus Damm Cc: linux-sh@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 5/5] arm64: renesas: r8a7795 dtsi: Add all MSIOF nodes Date: Thu, 27 Aug 2015 21:02:31 +0200 Message-Id: <1440702151-1406-6-git-send-email-geert+renesas@glider.be> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1440702151-1406-1-git-send-email-geert+renesas@glider.be> References: <1440702151-1406-1-git-send-email-geert+renesas@glider.be> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the device nodes for all MSIOF SPI controllers, incl. clocks, clock domain, and dma properties. Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 64 ++++++++++++++++++++++++++++++- include/dt-bindings/clock/r8a7795-clock.h | 4 ++ 2 files changed, 66 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 75908b8ccd6dc33a..b7db362536494385 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -272,7 +272,9 @@ <0 0xe6150040 0 4>; clocks = <&s3d4_clk>, <&s3d4_clk>, <&s3d4_clk>, <&s3d4_clk>, - <&s3d4_clk>; + <&s3d4_clk>, <&mso_clk>, + <&mso_clk>, <&mso_clk>, + <&mso_clk>; #clock-cells = <1>; renesas,clock-indices = < R8A7795_CLK_SCIF5 @@ -280,10 +282,16 @@ R8A7795_CLK_SCIF3 R8A7795_CLK_SCIF1 R8A7795_CLK_SCIF0 + R8A7795_CLK_MSIOF3 + R8A7795_CLK_MSIOF2 + R8A7795_CLK_MSIOF1 + R8A7795_CLK_MSIOF0 >; clock-output-names = "scif5", "scif4", "scif3", - "scif1", "scif0"; + "scif1", "scif0", + "msiof3", "msiof2", "msiof1", + "msiof0"; }; mstp3_clks: mstp3_clks@e615013c { @@ -481,6 +489,58 @@ status = "disabled"; }; + msiof0: spi@e6e90000 { + compatible = "renesas,msiof-r8a7795"; + reg = <0 0xe6e90000 0 0x0064>; + interrupts = ; + clocks = <&mstp2_clks R8A7795_CLK_MSIOF0>; + dmas = <&dmac1 0x41>, <&dmac1 0x40>; + dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6ea0000 { + compatible = "renesas,msiof-r8a7795"; + reg = <0 0xe6ea0000 0 0x0064>; + interrupts = ; + clocks = <&mstp2_clks R8A7795_CLK_MSIOF1>; + dmas = <&dmac1 0x43>, <&dmac1 0x42>; + dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof2: spi@e6c00000 { + compatible = "renesas,msiof-r8a7795"; + reg = <0 0xe6c00000 0 0x0064>; + interrupts = ; + clocks = <&mstp2_clks R8A7795_CLK_MSIOF2>; + dmas = <&dmac0 0x45>, <&dmac0 0x44>; + dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof3: spi@e6c10000 { + compatible = "renesas,msiof-r8a7795"; + reg = <0 0xe6c10000 0 0x0064>; + interrupts = ; + clocks = <&mstp2_clks R8A7795_CLK_MSIOF3>; + dmas = <&dmac0 0x47>, <&dmac0 0x46>; + dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + usb2_phy0: usb-phy@ee080200 { compatible = "renesas,usb2-phy-r8a7795"; reg = <0 0xee080200 0 0x6ff>, <0 0xe6590100 0 0x100>; diff --git a/include/dt-bindings/clock/r8a7795-clock.h b/include/dt-bindings/clock/r8a7795-clock.h index 2b8c375eebb6a9d9..91a7aad77534fa21 100644 --- a/include/dt-bindings/clock/r8a7795-clock.h +++ b/include/dt-bindings/clock/r8a7795-clock.h @@ -27,6 +27,10 @@ #define R8A7795_CLK_SCIF3 4 #define R8A7795_CLK_SCIF1 6 #define R8A7795_CLK_SCIF0 7 +#define R8A7795_CLK_MSIOF3 8 +#define R8A7795_CLK_MSIOF2 9 +#define R8A7795_CLK_MSIOF1 10 +#define R8A7795_CLK_MSIOF0 11 /* MSTP3 */ #define R8A7795_CLK_SCIF2 10