From patchwork Thu Sep 3 16:51:47 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 7117861 X-Patchwork-Delegate: horms@verge.net.au Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 106249F1D5 for ; Thu, 3 Sep 2015 16:51:52 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0F4D820764 for ; Thu, 3 Sep 2015 16:51:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AC44C2073B for ; Thu, 3 Sep 2015 16:51:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751335AbbICQvt (ORCPT ); Thu, 3 Sep 2015 12:51:49 -0400 Received: from baptiste.telenet-ops.be ([195.130.132.51]:40522 "EHLO baptiste.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751332AbbICQvs (ORCPT ); Thu, 3 Sep 2015 12:51:48 -0400 Received: from ayla.of.borg ([31.5.182.137]) by baptiste.telenet-ops.be with bizsmtp id Cgrl1r00T2yGKqv01grl6G; Thu, 03 Sep 2015 18:51:46 +0200 Received: from ramsan.of.borg ([192.168.97.29] helo=ramsan) by ayla.of.borg with esmtp (Exim 4.82) (envelope-from ) id 1ZXXjl-0006L8-9t; Thu, 03 Sep 2015 18:51:45 +0200 Received: from geert by ramsan with local (Exim 4.82) (envelope-from ) id 1ZXXjo-0002bG-RW; Thu, 03 Sep 2015 18:51:48 +0200 From: Geert Uytterhoeven To: Magnus Damm , Simon Horman , Kuninori Morimoto , Laurent Pinchart Cc: linux-sh@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH] [RFC] arm64: renesas: r8a7795: Complete SYS-DMAC nodes Date: Thu, 3 Sep 2015 18:51:47 +0200 Message-Id: <1441299107-9961-1-git-send-email-geert+renesas@glider.be> X-Mailer: git-send-email 1.9.1 Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Complete the dma-controller nodes for SYS-DMAC 0 to 2, incl. their MSTP clocks. Signed-off-by: Geert Uytterhoeven --- - Against today's topic/gen3-latest, - To be folded into "arm64: renesas: r8a7795 dtsi: Add dummy dma-controller nodes", - The datasheet states the SYS-DMAC parent clock is the "ZS" clock, which does not exist on R-Car Gen3 (on Gen2 that's the AXI clock). Hence I used "S2D1" (AXI-bus) instead. - Tested with MSIOF0 and spidev_test, without an SPI slave connected, - (H)SCIF1 DMA TX works, RX doesn't. --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 96 +++++++++++++++++++++++++++++-- include/dt-bindings/clock/r8a7795-clock.h | 3 + 2 files changed, 95 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index a2235400146289e2..caab7980d0a172ae 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -368,7 +368,8 @@ <0 0xe6150040 0 4>; clocks = <&s3d4_clk>, <&s3d4_clk>, <&s3d4_clk>, <&s3d4_clk>, - <&s3d4_clk>; + <&s3d4_clk>, <&s2d1_clk>, + <&s2d1_clk>, <&s2d1_clk>; #clock-cells = <1>; clock-indices = < R8A7795_CLK_SCIF5 @@ -376,6 +377,9 @@ R8A7795_CLK_SCIF3 R8A7795_CLK_SCIF1 R8A7795_CLK_SCIF0 + R8A7795_CLK_SYS_DMAC2 + R8A7795_CLK_SYS_DMAC1 + R8A7795_CLK_SYS_DMAC0 >; }; @@ -417,15 +421,99 @@ }; dmac0: dma-controller@e6700000 { - /* Empty node for now */ + compatible = "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&mstp2_clks R8A7795_CLK_SYS_DMAC0>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + #dma-cells = <1>; + dma-channels = <16>; }; dmac1: dma-controller@e7300000 { - /* Empty node for now */ + compatible = "renesas,rcar-dmac"; + reg = <0 0xe7300000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&mstp2_clks R8A7795_CLK_SYS_DMAC1>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + #dma-cells = <1>; + dma-channels = <16>; }; dmac2: dma-controller@e7310000 { - /* Empty node for now */ + compatible = "renesas,rcar-dmac"; + reg = <0 0xe7310000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&mstp2_clks R8A7795_CLK_SYS_DMAC2>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + #dma-cells = <1>; + dma-channels = <16>; }; scif0: serial@e6e60000 { diff --git a/include/dt-bindings/clock/r8a7795-clock.h b/include/dt-bindings/clock/r8a7795-clock.h index bf7fd98d59d9e739..9daeec8c4881dd2a 100644 --- a/include/dt-bindings/clock/r8a7795-clock.h +++ b/include/dt-bindings/clock/r8a7795-clock.h @@ -27,6 +27,9 @@ #define R8A7795_CLK_SCIF3 4 #define R8A7795_CLK_SCIF1 6 #define R8A7795_CLK_SCIF0 7 +#define R8A7795_CLK_SYS_DMAC2 17 +#define R8A7795_CLK_SYS_DMAC1 18 +#define R8A7795_CLK_SYS_DMAC0 19 /* MSTP3 */ #define R8A7795_CLK_SCIF2 10