diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 328f48bd15e711ad..e4cc66c0cf1fb4a5 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -1037,49 +1037,257 @@
 			compatible = "renesas,r8a7791-cpg-clocks",
 				     "renesas,rcar-gen2-cpg-clocks";
 			reg = <0 0xe6150000 0 0x1000>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
 			clocks = <&extal_clk &usb_extal_clk>;
 			#clock-cells = <1>;
 			clock-output-names = "main", "pll0", "pll1", "pll3",
 					     "lb", "qspi", "sdh", "sd0", "z",
 					     "rcan", "adsp";
 			#power-domain-cells = <0>;
-		};
 
-		/* Variable factor clocks */
-		sd2_clk: sd2_clk@e6150078 {
-			compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
-			reg = <0 0xe6150078 0 4>;
-			clocks = <&pll1_div2_clk>;
-			#clock-cells = <0>;
-			clock-output-names = "sd2";
-		};
-		sd3_clk: sd3_clk@e615026c {
-			compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
-			reg = <0 0xe615026c 0 4>;
-			clocks = <&pll1_div2_clk>;
-			#clock-cells = <0>;
-			clock-output-names = "sd3";
-		};
-		mmc0_clk: mmc0_clk@e6150240 {
-			compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
-			reg = <0 0xe6150240 0 4>;
-			clocks = <&pll1_div2_clk>;
-			#clock-cells = <0>;
-			clock-output-names = "mmc0";
-		};
-		ssp_clk: ssp_clk@e6150248 {
-			compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
-			reg = <0 0xe6150248 0 4>;
-			clocks = <&pll1_div2_clk>;
-			#clock-cells = <0>;
-			clock-output-names = "ssp";
-		};
-		ssprs_clk: ssprs_clk@e615024c {
-			compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
-			reg = <0 0xe615024c 0 4>;
-			clocks = <&pll1_div2_clk>;
-			#clock-cells = <0>;
-			clock-output-names = "ssprs";
+			/* Variable factor clocks */
+			sd2_clk: sd2_clk@e6150078 {
+				compatible = "renesas,r8a7791-div6-clock",
+					     "renesas,cpg-div6-clock";
+				reg = <0 0xe6150078 0 4>;
+				clocks = <&pll1_div2_clk>;
+				#clock-cells = <0>;
+				clock-output-names = "sd2";
+			};
+			sd3_clk: sd3_clk@e615026c {
+				compatible = "renesas,r8a7791-div6-clock",
+					     "renesas,cpg-div6-clock";
+				reg = <0 0xe615026c 0 4>;
+				clocks = <&pll1_div2_clk>;
+				#clock-cells = <0>;
+				clock-output-names = "sd3";
+			};
+			mmc0_clk: mmc0_clk@e6150240 {
+				compatible = "renesas,r8a7791-div6-clock",
+					     "renesas,cpg-div6-clock";
+				reg = <0 0xe6150240 0 4>;
+				clocks = <&pll1_div2_clk>;
+				#clock-cells = <0>;
+				clock-output-names = "mmc0";
+			};
+			ssp_clk: ssp_clk@e6150248 {
+				compatible = "renesas,r8a7791-div6-clock",
+					     "renesas,cpg-div6-clock";
+				reg = <0 0xe6150248 0 4>;
+				clocks = <&pll1_div2_clk>;
+				#clock-cells = <0>;
+				clock-output-names = "ssp";
+			};
+			ssprs_clk: ssprs_clk@e615024c {
+				compatible = "renesas,r8a7791-div6-clock",
+					     "renesas,cpg-div6-clock";
+				reg = <0 0xe615024c 0 4>;
+				clocks = <&pll1_div2_clk>;
+				#clock-cells = <0>;
+				clock-output-names = "ssprs";
+			};
+
+			/* Gate clocks */
+			mstp0_clks: mstp0_clks@e6150130 {
+				compatible = "renesas,r8a7791-mstp-clocks",
+					     "renesas,cpg-mstp-clocks";
+				reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
+				clocks = <&mp_clk>;
+				#clock-cells = <1>;
+				clock-indices = <R8A7791_CLK_MSIOF0>;
+				clock-output-names = "msiof0";
+			};
+			mstp1_clks: mstp1_clks@e6150134 {
+				compatible = "renesas,r8a7791-mstp-clocks",
+					     "renesas,cpg-mstp-clocks";
+				reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
+				clocks = <&zs_clk>, <&zs_clk>, <&m2_clk>, <&zs_clk>, <&p_clk>,
+					 <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
+					 <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>,
+					 <&zs_clk>;
+				#clock-cells = <1>;
+				clock-indices = <
+					R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU
+					R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG
+					R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0
+					R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 R8A7791_CLK_CMT0
+					R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 R8A7791_CLK_VSP1_DU0
+					R8A7791_CLK_VSP1_S
+				>;
+				clock-output-names =
+					"vcp0", "vpc0", "jpu", "ssp1", "tmu1", "3dg",
+					"2ddmac", "fdp1-1", "fdp1-0", "tmu3", "tmu2", "cmt0",
+					"tmu0", "vsp1-du1", "vsp1-du0", "vsp1-sy";
+			};
+			mstp2_clks: mstp2_clks@e6150138 {
+				compatible = "renesas,r8a7791-mstp-clocks",
+					     "renesas,cpg-mstp-clocks";
+				reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
+				clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
+					 <&mp_clk>, <&mp_clk>, <&mp_clk>,
+					 <&zs_clk>, <&zs_clk>;
+				#clock-cells = <1>;
+				clock-indices = <
+					R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
+					R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
+					R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
+					R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0
+				>;
+				clock-output-names =
+					"scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
+					"scifb1", "msiof1", "scifb2",
+					"sys-dmac1", "sys-dmac0";
+			};
+			mstp3_clks: mstp3_clks@e615013c {
+				compatible = "renesas,r8a7791-mstp-clocks",
+					     "renesas,cpg-mstp-clocks";
+				reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
+				clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
+					 <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
+					 <&hp_clk>, <&hp_clk>;
+				#clock-cells = <1>;
+				clock-indices = <
+					R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
+					R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1
+					R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
+					R8A7791_CLK_USBDMAC0 R8A7791_CLK_USBDMAC1
+				>;
+				clock-output-names =
+					"tpu0", "sdhi2", "sdhi1", "sdhi0",
+					"mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1",
+					"usbdmac0", "usbdmac1";
+			};
+			mstp4_clks: mstp4_clks@e6150140 {
+				compatible = "renesas,r8a7791-mstp-clocks",
+					     "renesas,cpg-mstp-clocks";
+				reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
+				clocks = <&cp_clk>;
+				#clock-cells = <1>;
+				clock-indices = <R8A7791_CLK_IRQC>;
+				clock-output-names = "irqc";
+			};
+			mstp5_clks: mstp5_clks@e6150144 {
+				compatible = "renesas,r8a7791-mstp-clocks",
+					     "renesas,cpg-mstp-clocks";
+				reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
+				clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7791_CLK_ADSP>,
+					 <&extal_clk>, <&p_clk>;
+				#clock-cells = <1>;
+				clock-indices = <
+					R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1
+					R8A7791_CLK_ADSP_MOD R8A7791_CLK_THERMAL
+					R8A7791_CLK_PWM
+				>;
+				clock-output-names = "audmac0", "audmac1", "adsp_mod",
+						     "thermal", "pwm";
+			};
+			mstp7_clks: mstp7_clks@e615014c {
+				compatible = "renesas,r8a7791-mstp-clocks",
+					     "renesas,cpg-mstp-clocks";
+				reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
+				clocks = <&mp_clk>,  <&hp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
+					 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
+					 <&zx_clk>, <&zx_clk>, <&zx_clk>;
+				#clock-cells = <1>;
+				clock-indices = <
+					R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
+					R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
+					R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
+					R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
+					R8A7791_CLK_LVDS0
+				>;
+				clock-output-names =
+					"ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
+					"scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
+			};
+			mstp8_clks: mstp8_clks@e6150990 {
+				compatible = "renesas,r8a7791-mstp-clocks",
+					     "renesas,cpg-mstp-clocks";
+				reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
+				clocks = <&zx_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>,
+					 <&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>;
+				#clock-cells = <1>;
+				clock-indices = <
+					R8A7791_CLK_IPMMU_SGX R8A7791_CLK_MLB
+					R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
+					R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
+				>;
+				clock-output-names =
+					"ipmmu_sgx", "mlb", "vin2", "vin1", "vin0", "ether",
+					"sata1", "sata0";
+			};
+			mstp9_clks: mstp9_clks@e6150994 {
+				compatible = "renesas,r8a7791-mstp-clocks",
+					     "renesas,cpg-mstp-clocks";
+				reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
+				clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
+					 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
+					 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>,
+					 <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
+					 <&hp_clk>, <&hp_clk>;
+				#clock-cells = <1>;
+				clock-indices = <
+					R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4
+					R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0
+					R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5
+					R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2
+					R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
+				>;
+				clock-output-names =
+					"gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
+					"rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2",
+					"i2c1", "i2c0";
+			};
+			mstp10_clks: mstp10_clks@e6150998 {
+				compatible = "renesas,r8a7791-mstp-clocks",
+					     "renesas,cpg-mstp-clocks";
+				reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
+				clocks = <&p_clk>,
+					<&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
+					<&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
+					<&p_clk>,
+					<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
+					<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
+					<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
+					<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
+					<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
+					<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
+					<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>;
+
+				#clock-cells = <1>;
+				clock-indices = <
+					R8A7791_CLK_SSI_ALL
+					R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5
+					R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0
+					R8A7791_CLK_SCU_ALL
+					R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0
+					R8A7791_CLK_SCU_CTU1_MIX1 R8A7791_CLK_SCU_CTU0_MIX0
+					R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5
+					R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0
+				>;
+				clock-output-names =
+					"ssi-all",
+					"ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
+					"ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
+					"scu-all",
+					"scu-dvc1", "scu-dvc0",
+					"scu-ctu1-mix1", "scu-ctu0-mix0",
+					"scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
+					"scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
+			};
+			mstp11_clks: mstp11_clks@e615099c {
+				compatible = "renesas,r8a7791-mstp-clocks",
+					     "renesas,cpg-mstp-clocks";
+				reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
+				clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
+				#clock-cells = <1>;
+				clock-indices = <
+					R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
+				>;
+				clock-output-names = "scifa3", "scifa4", "scifa5";
+			};
 		};
 
 		/* Fixed factor clocks */
@@ -1228,194 +1436,6 @@
 			clock-output-names = "cp";
 		};
 
-		/* Gate clocks */
-		mstp0_clks: mstp0_clks@e6150130 {
-			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
-			reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
-			clocks = <&mp_clk>;
-			#clock-cells = <1>;
-			clock-indices = <R8A7791_CLK_MSIOF0>;
-			clock-output-names = "msiof0";
-		};
-		mstp1_clks: mstp1_clks@e6150134 {
-			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
-			reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
-			clocks = <&zs_clk>, <&zs_clk>, <&m2_clk>, <&zs_clk>, <&p_clk>,
-				 <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
-				 <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>,
-				 <&zs_clk>;
-			#clock-cells = <1>;
-			clock-indices = <
-				R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU
-				R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG
-				R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0
-				R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 R8A7791_CLK_CMT0
-				R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 R8A7791_CLK_VSP1_DU0
-				R8A7791_CLK_VSP1_S
-			>;
-			clock-output-names =
-				"vcp0", "vpc0", "jpu", "ssp1", "tmu1", "3dg",
-				"2ddmac", "fdp1-1", "fdp1-0", "tmu3", "tmu2", "cmt0",
-				"tmu0", "vsp1-du1", "vsp1-du0", "vsp1-sy";
-		};
-		mstp2_clks: mstp2_clks@e6150138 {
-			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
-			reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
-			clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
-				 <&mp_clk>, <&mp_clk>, <&mp_clk>,
-				 <&zs_clk>, <&zs_clk>;
-			#clock-cells = <1>;
-			clock-indices = <
-				R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
-				R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
-				R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
-				R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0
-			>;
-			clock-output-names =
-				"scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
-				"scifb1", "msiof1", "scifb2",
-				"sys-dmac1", "sys-dmac0";
-		};
-		mstp3_clks: mstp3_clks@e615013c {
-			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
-			reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
-			clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
-				 <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
-				 <&hp_clk>, <&hp_clk>;
-			#clock-cells = <1>;
-			clock-indices = <
-				R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
-				R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1
-				R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
-				R8A7791_CLK_USBDMAC0 R8A7791_CLK_USBDMAC1
-			>;
-			clock-output-names =
-				"tpu0", "sdhi2", "sdhi1", "sdhi0",
-				"mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1",
-				"usbdmac0", "usbdmac1";
-		};
-		mstp4_clks: mstp4_clks@e6150140 {
-			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
-			reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
-			clocks = <&cp_clk>;
-			#clock-cells = <1>;
-			clock-indices = <R8A7791_CLK_IRQC>;
-			clock-output-names = "irqc";
-		};
-		mstp5_clks: mstp5_clks@e6150144 {
-			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
-			reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
-			clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7791_CLK_ADSP>,
-				 <&extal_clk>, <&p_clk>;
-			#clock-cells = <1>;
-			clock-indices = <
-				R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1
-				R8A7791_CLK_ADSP_MOD R8A7791_CLK_THERMAL
-				R8A7791_CLK_PWM
-			>;
-			clock-output-names = "audmac0", "audmac1", "adsp_mod",
-					     "thermal", "pwm";
-		};
-		mstp7_clks: mstp7_clks@e615014c {
-			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
-			reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
-			clocks = <&mp_clk>,  <&hp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
-				 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
-				 <&zx_clk>, <&zx_clk>, <&zx_clk>;
-			#clock-cells = <1>;
-			clock-indices = <
-				R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
-				R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
-				R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
-				R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
-				R8A7791_CLK_LVDS0
-			>;
-			clock-output-names =
-				"ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
-				"scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
-		};
-		mstp8_clks: mstp8_clks@e6150990 {
-			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
-			reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
-			clocks = <&zx_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>,
-			         <&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>;
-			#clock-cells = <1>;
-			clock-indices = <
-				R8A7791_CLK_IPMMU_SGX R8A7791_CLK_MLB
-				R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
-				R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
-			>;
-			clock-output-names =
-				"ipmmu_sgx", "mlb", "vin2", "vin1", "vin0", "ether",
-				"sata1", "sata0";
-		};
-		mstp9_clks: mstp9_clks@e6150994 {
-			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
-			reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
-			clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
-				 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
-				 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>,
-				 <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
-				 <&hp_clk>, <&hp_clk>;
-			#clock-cells = <1>;
-			clock-indices = <
-				R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4
-				R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0
-				R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5
-				R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2
-				R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
-			>;
-			clock-output-names =
-				"gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
-				"rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2",
-				"i2c1", "i2c0";
-		};
-		mstp10_clks: mstp10_clks@e6150998 {
-			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
-			reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
-			clocks = <&p_clk>,
-				<&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
-				<&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
-				<&p_clk>,
-				<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
-				<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
-				<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
-				<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
-				<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
-				<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
-				<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>;
-
-			#clock-cells = <1>;
-			clock-indices = <
-				R8A7791_CLK_SSI_ALL
-				R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5
-				R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0
-				R8A7791_CLK_SCU_ALL
-				R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0
-				R8A7791_CLK_SCU_CTU1_MIX1 R8A7791_CLK_SCU_CTU0_MIX0
-				R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5
-				R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0
-			>;
-			clock-output-names =
-				"ssi-all",
-				"ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
-				"ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
-				"scu-all",
-				"scu-dvc1", "scu-dvc0",
-				"scu-ctu1-mix1", "scu-ctu0-mix0",
-				"scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
-				"scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
-		};
-		mstp11_clks: mstp11_clks@e615099c {
-			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
-			reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
-			clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
-			#clock-cells = <1>;
-			clock-indices = <
-				R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
-			>;
-			clock-output-names = "scifa3", "scifa4", "scifa5";
-		};
 	};
 
 	qspi: spi@e6b10000 {
