From patchwork Thu Oct 15 06:23:57 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 7402291 X-Patchwork-Delegate: horms@verge.net.au Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id BF375BEEA4 for ; Thu, 15 Oct 2015 06:25:00 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CB138209E7 for ; Thu, 15 Oct 2015 06:24:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BA4B0209EF for ; Thu, 15 Oct 2015 06:24:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753671AbbJOGYx (ORCPT ); Thu, 15 Oct 2015 02:24:53 -0400 Received: from kirsty.vergenet.net ([202.4.237.240]:36130 "EHLO kirsty.vergenet.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754025AbbJOGYm (ORCPT ); Thu, 15 Oct 2015 02:24:42 -0400 Received: from reginn.isobedori.kobe.vergenet.net (p2250-ipbfp1101kobeminato.hyogo.ocn.ne.jp [122.22.210.250]) by kirsty.vergenet.net (Postfix) with ESMTPA id DF37825B7A0; Thu, 15 Oct 2015 17:24:36 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=verge.net.au; s=mail; t=1444890277; bh=EA7LQ9YiY6nLqA0+c3VYNNvX+XIVPnrREmCR/QUtbu0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=esNeSqoLQPR719MYxNoVbXZTf9og43Ukm7v8WPMTFrMTkVo+SdKegYTFTFAcDNhXT 5B1nN0FUG9i8KCo/esRogqwy40vat7QTfvxeRyFbrWQFKpUXKx8Cfw95TlK9XRbZGs 45Uh69Bv4blpa+z6TIkQkBG23CydTLtcxlGaApXU= Received: by reginn.isobedori.kobe.vergenet.net (Postfix, from userid 7100) id BD6F99405AE; Thu, 15 Oct 2015 15:24:35 +0900 (JST) From: Simon Horman To: linux-sh@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Magnus Damm Subject: [PATCH v11 2/8] arm64: renesas: r8a7795 dtsi: Add all common divider clocks Date: Thu, 15 Oct 2015 15:23:57 +0900 Message-Id: <1444890243-6978-3-git-send-email-horms+renesas@verge.net.au> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1444890243-6978-1-git-send-email-horms+renesas@verge.net.au> References: <1444890243-6978-1-git-send-email-horms+renesas@verge.net.au> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID,T_RP_MATCHES_RCVD,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Geert Uytterhoeven Add all clocks generated from PLL1 by the CPG common divider block. Signed-off-by: Geert Uytterhoeven Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- Changes since v10: - None Changes since V9: (Magnus Damm ) - Introduce pll1_div2 by folding in earlier posted patch: [PATCH][RFC] arm64: renesas: r8a7795 dtsi: Update common divider clocks Changes since V8: (Magnus Damm ) - Updated commit message. Changes since V7: (Magnus Damm ) - Folded in s3d4_clk - Reordered to apply without SCIF bits Based on: [PATCH 3/3] arm64: renesas: r8a7795 dtsi: Add all common divider clocks --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 169 +++++++++++++++++++++++++++++++ 1 file changed, 169 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index ff6e0e98664a..77f93a77aa79 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -70,6 +70,175 @@ #clock-cells = <1>; ranges; + /* Fixed factor clocks */ + pll1_div2_clk: pll1_div2 { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7795_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + + zt_clk: zt { + compatible = "fixed-factor-clock"; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + }; + + ztr_clk: ztr { + compatible = "fixed-factor-clock"; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-div = <6>; + clock-mult = <1>; + }; + + ztrd2_clk: ztrd2 { + compatible = "fixed-factor-clock"; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-div = <12>; + clock-mult = <1>; + }; + + zx_clk: zx { + compatible = "fixed-factor-clock"; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + + s0_clk: s0 { + compatible = "fixed-factor-clock"; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + + s0d1_clk: s0d1 { + compatible = "fixed-factor-clock"; + clocks = <&s0_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + + s0d4_clk: s0d4 { + compatible = "fixed-factor-clock"; + clocks = <&s0_clk>; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + }; + + s1_clk: s1 { + compatible = "fixed-factor-clock"; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-div = <3>; + clock-mult = <1>; + }; + + s1d1_clk: s1d1 { + compatible = "fixed-factor-clock"; + clocks = <&s1_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + + s1d2_clk: s1d2 { + compatible = "fixed-factor-clock"; + clocks = <&s1_clk>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + + s1d4_clk: s1d4 { + compatible = "fixed-factor-clock"; + clocks = <&s1_clk>; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + }; + + s2_clk: s2 { + compatible = "fixed-factor-clock"; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + }; + + s2d1_clk: s2d1 { + compatible = "fixed-factor-clock"; + clocks = <&s2_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + + s2d2_clk: s2d2 { + compatible = "fixed-factor-clock"; + clocks = <&s2_clk>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + + s2d4_clk: s2d4 { + compatible = "fixed-factor-clock"; + clocks = <&s2_clk>; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + }; + + s3_clk: s3 { + compatible = "fixed-factor-clock"; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-div = <6>; + clock-mult = <1>; + }; + + s3d1_clk: s3d1 { + compatible = "fixed-factor-clock"; + clocks = <&s3_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + + s3d2_clk: s3d2 { + compatible = "fixed-factor-clock"; + clocks = <&s3_clk>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + + s3d4_clk: s3d4 { + compatible = "fixed-factor-clock"; + clocks = <&s3_clk>; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + }; + + cl_clk: cl { + compatible = "fixed-factor-clock"; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-div = <48>; + clock-mult = <1>; + }; + cpg_clocks: cpg_clocks@e6150000 { compatible = "renesas,r8a7795-cpg-clocks", "renesas,rcar-gen3-cpg-clocks";