From patchwork Fri Oct 16 12:49:17 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 7414631 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 3CF139F4DC for ; Fri, 16 Oct 2015 12:49:32 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6654020A6F for ; Fri, 16 Oct 2015 12:49:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 68D7F20A6C for ; Fri, 16 Oct 2015 12:49:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752308AbbJPMt2 (ORCPT ); Fri, 16 Oct 2015 08:49:28 -0400 Received: from laurent.telenet-ops.be ([195.130.137.89]:57183 "EHLO laurent.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754015AbbJPMt0 (ORCPT ); Fri, 16 Oct 2015 08:49:26 -0400 Received: from ayla.of.borg ([84.195.106.123]) by laurent.telenet-ops.be with bizsmtp id VopK1r00M2fm56U01opK0W; Fri, 16 Oct 2015 14:49:24 +0200 Received: from ramsan.of.borg ([192.168.97.29] helo=ramsan) by ayla.of.borg with esmtp (Exim 4.82) (envelope-from ) id 1Zn4Rj-0003PB-6H; Fri, 16 Oct 2015 14:49:19 +0200 Received: from geert by ramsan with local (Exim 4.82) (envelope-from ) id 1Zn4Rm-00046v-MF; Fri, 16 Oct 2015 14:49:22 +0200 From: Geert Uytterhoeven To: Michael Turquette , Stephen Boyd , Laurent Pinchart , Magnus Damm , Simon Horman , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-sh@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v4 2/5] [RFC] clk: shmobile: Add r8a7795 CPG Core Clock Definitions Date: Fri, 16 Oct 2015 14:49:17 +0200 Message-Id: <1444999760-15750-3-git-send-email-geert+renesas@glider.be> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1444999760-15750-1-git-send-email-geert+renesas@glider.be> References: <1444999760-15750-1-git-send-email-geert+renesas@glider.be> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add all R-Car H3 CPG Core Clock Outputs defined in the datasheet. Signed-off-by: Geert Uytterhoeven Reviewed-by: Magnus Damm Reviewed-by: Laurent Pinchart --- v4: - Add all clocks instead of just the ones used by the current DTS. v3: - New. --- include/dt-bindings/clock/r8a7795-cpg-mssr.h | 63 ++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 include/dt-bindings/clock/r8a7795-cpg-mssr.h diff --git a/include/dt-bindings/clock/r8a7795-cpg-mssr.h b/include/dt-bindings/clock/r8a7795-cpg-mssr.h new file mode 100644 index 0000000000000000..e864aae0a2561c4b --- /dev/null +++ b/include/dt-bindings/clock/r8a7795-cpg-mssr.h @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2015 Renesas Electronics Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ + +#include + +/* r8a7795 CPG Core Clocks */ +#define R8A7795_CLK_Z 0 +#define R8A7795_CLK_Z2 1 +#define R8A7795_CLK_ZR 2 +#define R8A7795_CLK_ZG 3 +#define R8A7795_CLK_ZTR 4 +#define R8A7795_CLK_ZTRD2 5 +#define R8A7795_CLK_ZT 6 +#define R8A7795_CLK_ZX 7 +#define R8A7795_CLK_S0D1 8 +#define R8A7795_CLK_S0D4 9 +#define R8A7795_CLK_S1D1 10 +#define R8A7795_CLK_S1D2 11 +#define R8A7795_CLK_S1D4 12 +#define R8A7795_CLK_S2D1 13 +#define R8A7795_CLK_S2D2 14 +#define R8A7795_CLK_S2D4 15 +#define R8A7795_CLK_S3D1 16 +#define R8A7795_CLK_S3D2 17 +#define R8A7795_CLK_S3D4 18 +#define R8A7795_CLK_LB 19 +#define R8A7795_CLK_CL 20 +#define R8A7795_CLK_ZB3 21 +#define R8A7795_CLK_ZB3D2 22 +#define R8A7795_CLK_CR 23 +#define R8A7795_CLK_CRD2 24 +#define R8A7795_CLK_SD0H 25 +#define R8A7795_CLK_SD0 26 +#define R8A7795_CLK_SD1H 27 +#define R8A7795_CLK_SD1 28 +#define R8A7795_CLK_SD2H 29 +#define R8A7795_CLK_SD2 30 +#define R8A7795_CLK_SD3H 31 +#define R8A7795_CLK_SD3 32 +#define R8A7795_CLK_SSP2 33 +#define R8A7795_CLK_SSP1 34 +#define R8A7795_CLK_SSPRS 35 +#define R8A7795_CLK_RPC 36 +#define R8A7795_CLK_RPCD2 37 +#define R8A7795_CLK_MSO 38 +#define R8A7795_CLK_CANFD 39 +#define R8A7795_CLK_HDMI 40 +#define R8A7795_CLK_CSI0 41 +#define R8A7795_CLK_CSIREF 42 +#define R8A7795_CLK_CP 43 +#define R8A7795_CLK_CPEX 44 +#define R8A7795_CLK_R 45 +#define R8A7795_CLK_OSC 46 + +#endif /* __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ */