From patchwork Mon Nov 30 14:16:51 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 7726251 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id D103C9F1C2 for ; Mon, 30 Nov 2015 14:17:05 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DBFC320532 for ; Mon, 30 Nov 2015 14:17:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E330420529 for ; Mon, 30 Nov 2015 14:17:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754256AbbK3ORA (ORCPT ); Mon, 30 Nov 2015 09:17:00 -0500 Received: from baptiste.telenet-ops.be ([195.130.132.51]:57691 "EHLO baptiste.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753853AbbK3OQ7 (ORCPT ); Mon, 30 Nov 2015 09:16:59 -0500 Received: from ayla.of.borg ([84.195.106.123]) by baptiste.telenet-ops.be with bizsmtp id nqGx1r00t2fm56U01qGxdG; Mon, 30 Nov 2015 15:16:58 +0100 Received: from ramsan.of.borg ([192.168.97.29] helo=ramsan) by ayla.of.borg with esmtp (Exim 4.82) (envelope-from ) id 1a3PGD-00087B-NF; Mon, 30 Nov 2015 15:16:57 +0100 Received: from geert by ramsan with local (Exim 4.82) (envelope-from ) id 1a3PGD-0002DF-S8; Mon, 30 Nov 2015 15:16:57 +0100 From: Geert Uytterhoeven To: Simon Horman , Magnus Damm Cc: linux-sh@vger.kernel.org, devicetree@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 1/2] ARM: shmobile: sh73a0: Add MSIOF clocks Date: Mon, 30 Nov 2015 15:16:51 +0100 Message-Id: <1448893012-8465-2-git-send-email-geert+renesas@glider.be> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1448893012-8465-1-git-send-email-geert+renesas@glider.be> References: <1448893012-8465-1-git-send-email-geert+renesas@glider.be> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The 4 MSIOF clocks are MSTP clocks, and children of the SUB clock. Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/sh73a0.dtsi | 28 ++++++++++++++++------------ include/dt-bindings/clock/sh73a0-clock.h | 6 +++++- 2 files changed, 21 insertions(+), 13 deletions(-) diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index f90ef9c93d3df3aa..c55b09e640f0b7d3 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -812,13 +812,13 @@ mstp0_clks: mstp0_clks@e6150130 { compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0xe6150130 4>, <0xe6150030 4>; - clocks = <&cpg_clocks SH73A0_CLK_HP>; + clocks = <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>; #clock-cells = <1>; clock-indices = < - SH73A0_CLK_IIC2 + SH73A0_CLK_IIC2 SH73A0_CLK_MSIOF0 >; clock-output-names = - "iic2"; + "iic2", "msiof0"; }; mstp1_clks: mstp1_clks@e6150134 { compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; @@ -848,20 +848,24 @@ reg = <0xe6150138 4>, <0xe6150040 4>; clocks = <&sub_clk>, <&cpg_clocks SH73A0_CLK_HP>, <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>, - <&sub_clk>, <&sub_clk>, <&sub_clk>, <&sub_clk>, - <&sub_clk>, <&sub_clk>; + <&sub_clk>, <&sub_clk>, <&sub_clk>, + <&sub_clk>, <&sub_clk>, <&sub_clk>, + <&sub_clk>, <&sub_clk>, <&sub_clk>; #clock-cells = <1>; clock-indices = < SH73A0_CLK_SCIFA7 SH73A0_CLK_SY_DMAC - SH73A0_CLK_MP_DMAC SH73A0_CLK_SCIFA5 - SH73A0_CLK_SCIFB SH73A0_CLK_SCIFA0 - SH73A0_CLK_SCIFA1 SH73A0_CLK_SCIFA2 - SH73A0_CLK_SCIFA3 SH73A0_CLK_SCIFA4 + SH73A0_CLK_MP_DMAC SH73A0_CLK_MSIOF3 + SH73A0_CLK_MSIOF1 SH73A0_CLK_SCIFA5 + SH73A0_CLK_SCIFB SH73A0_CLK_MSIOF2 + SH73A0_CLK_SCIFA0 SH73A0_CLK_SCIFA1 + SH73A0_CLK_SCIFA2 SH73A0_CLK_SCIFA3 + SH73A0_CLK_SCIFA4 >; clock-output-names = - "scifa7", "sy_dmac", "mp_dmac", "scifa5", - "scifb", "scifa0", "scifa1", "scifa2", - "scifa3", "scifa4"; + "scifa7", "sy_dmac", "mp_dmac", "msiof3", + "msiof1", "scifa5", "scifb", "msiof2", + "scifa0", "scifa1", "scifa2", "scifa3", + "scifa4"; }; mstp3_clks: mstp3_clks@e615013c { compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; diff --git a/include/dt-bindings/clock/sh73a0-clock.h b/include/dt-bindings/clock/sh73a0-clock.h index 53369568c24c5dc6..2eca353a29d74bc6 100644 --- a/include/dt-bindings/clock/sh73a0-clock.h +++ b/include/dt-bindings/clock/sh73a0-clock.h @@ -28,7 +28,8 @@ #define SH73A0_CLK_HP 14 /* MSTP0 */ -#define SH73A0_CLK_IIC2 1 +#define SH73A0_CLK_IIC2 1 +#define SH73A0_CLK_MSIOF0 0 /* MSTP1 */ #define SH73A0_CLK_CEU1 29 @@ -45,8 +46,11 @@ #define SH73A0_CLK_SCIFA7 19 #define SH73A0_CLK_SY_DMAC 18 #define SH73A0_CLK_MP_DMAC 17 +#define SH73A0_CLK_MSIOF3 15 +#define SH73A0_CLK_MSIOF1 8 #define SH73A0_CLK_SCIFA5 7 #define SH73A0_CLK_SCIFB 6 +#define SH73A0_CLK_MSIOF2 5 #define SH73A0_CLK_SCIFA0 4 #define SH73A0_CLK_SCIFA1 3 #define SH73A0_CLK_SCIFA2 2