From patchwork Mon Dec 7 18:24:14 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 7789011 X-Patchwork-Delegate: horms@verge.net.au Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 000489F1C2 for ; Mon, 7 Dec 2015 18:25:04 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2E90C2053D for ; Mon, 7 Dec 2015 18:25:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5C1F42054B for ; Mon, 7 Dec 2015 18:25:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755967AbbLGSZA (ORCPT ); Mon, 7 Dec 2015 13:25:00 -0500 Received: from [195.130.132.51] ([195.130.132.51]:36160 "EHLO baptiste.telenet-ops.be" rhost-flags-FAIL-FAIL-OK-OK) by vger.kernel.org with ESMTP id S1755901AbbLGSY6 (ORCPT ); Mon, 7 Dec 2015 13:24:58 -0500 Received: from ayla.of.borg ([84.195.106.123]) by baptiste.telenet-ops.be with bizsmtp id qiQT1r00Y2fm56U01iQTBF; Mon, 07 Dec 2015 19:24:35 +0100 Received: from ramsan.of.borg ([192.168.97.29] helo=ramsan) by ayla.of.borg with esmtp (Exim 4.82) (envelope-from ) id 1a60SZ-00036Z-1a; Mon, 07 Dec 2015 19:24:27 +0100 Received: from geert by ramsan with local (Exim 4.82) (envelope-from ) id 1a60Sa-0004Lv-N4; Mon, 07 Dec 2015 19:24:28 +0100 From: Geert Uytterhoeven To: Simon Horman , Magnus Damm Cc: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Catalin Marinas , Will Deacon , Sudeep Holla , Lina Iyer , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-sh@vger.kernel.org, linux-pm@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 1/6] ARM: shmobile: r8a73a4 dtsi: Add L2 cache-controller nodes Date: Mon, 7 Dec 2015 19:24:14 +0100 Message-Id: <1449512659-16688-2-git-send-email-geert+renesas@glider.be> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1449512659-16688-1-git-send-email-geert+renesas@glider.be> References: <1449512659-16688-1-git-send-email-geert+renesas@glider.be> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add device nodes for the L2 caches, and link the CPU node to its L2 cache node. The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as 64 KiB x 16 ways), and located in PM domain A3SM. It requires the following settings: - Tag RAM latency: 3 cycles, - Data RAM latency: 4 cycles. The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as 64 KiB x 8 ways), and located in PM domain A3KM. Signed-off-by: Geert Uytterhoeven --- What are the DT bindings for Cortex-A15/A7 L2 cache controllers? v2: - New. --- arch/arm/boot/dts/r8a73a4.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index 86fab56cd6314df7..73f7ea3cb2209a00 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -29,6 +29,7 @@ reg = <0>; clock-frequency = <1500000000>; power-domains = <&pd_a2sl>; + next-level-cache = <&L2_CA15>; }; }; @@ -45,6 +46,24 @@ <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; + L2_CA15: cache-controller@0 { + compatible = "cache"; + clocks = <&cpg_clocks R8A73A4_CLK_Z>; + power-domains = <&pd_a3sm>; + arm,data-latency = <4 4 0>; + arm,tag-latency = <3 3 3>; + cache-unified; + cache-level = <2>; + }; + + L2_CA7: cache-controller@1 { + compatible = "cache"; + clocks = <&cpg_clocks R8A73A4_CLK_Z2>; + power-domains = <&pd_a3km>; + cache-unified; + cache-level = <2>; + }; + dbsc1: memory-controller@e6790000 { compatible = "renesas,dbsc-r8a73a4"; reg = <0 0xe6790000 0 0x10000>;