From patchwork Mon Dec 7 18:24:15 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 7788971 X-Patchwork-Delegate: horms@verge.net.au Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 92249BEEE1 for ; Mon, 7 Dec 2015 18:24:41 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8F1AF2054E for ; Mon, 7 Dec 2015 18:24:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D16F320551 for ; Mon, 7 Dec 2015 18:24:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755826AbbLGSYg (ORCPT ); Mon, 7 Dec 2015 13:24:36 -0500 Received: from michel.telenet-ops.be ([195.130.137.88]:47094 "EHLO michel.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755656AbbLGSYf (ORCPT ); Mon, 7 Dec 2015 13:24:35 -0500 Received: from ayla.of.borg ([84.195.106.123]) by michel.telenet-ops.be with bizsmtp id qiQT1r00Q2fm56U06iQTqQ; Mon, 07 Dec 2015 19:24:34 +0100 Received: from ramsan.of.borg ([192.168.97.29] helo=ramsan) by ayla.of.borg with esmtp (Exim 4.82) (envelope-from ) id 1a60SZ-00036d-1a; Mon, 07 Dec 2015 19:24:27 +0100 Received: from geert by ramsan with local (Exim 4.82) (envelope-from ) id 1a60Sa-0004Lz-Nv; Mon, 07 Dec 2015 19:24:28 +0100 From: Geert Uytterhoeven To: Simon Horman , Magnus Damm Cc: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Catalin Marinas , Will Deacon , Sudeep Holla , Lina Iyer , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-sh@vger.kernel.org, linux-pm@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 2/6] ARM: shmobile: r8a7790 dtsi: Add L2 cache-controller nodes Date: Mon, 7 Dec 2015 19:24:15 +0100 Message-Id: <1449512659-16688-3-git-send-email-geert+renesas@glider.be> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1449512659-16688-1-git-send-email-geert+renesas@glider.be> References: <1449512659-16688-1-git-send-email-geert+renesas@glider.be> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add device nodes for the L2 caches, and link the CPU nodes to them. The L2 cache for the Cortex-A15 CPU cores is 2 MiB large (organized as 128 KiB x 16 ways), and requires the following settings: - Tag RAM latency: 3 cycles, - Data RAM latency: 4 cycles, - Data RAM setup: 1 cycle. The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as 64 KiB x 8 ways). Signed-off-by: Geert Uytterhoeven --- What are the DT bindings for Cortex-A15/A7 L2 cache controllers? v2: - Drop (incorrect) optional cache-{size,sets,{block,line}-size} properties, as this information is auto-detected, - Integrate linking CPUs to L2 caches into this patch, - Extracted from series "[PATCH/RFC 00/15] ARM: shmobile: R-Car: Add SYSC PM Domain DT Support". --- arch/arm/boot/dts/r8a7790.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 6cfd0dc79bbec067..ef5d46faef0c5975 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -52,6 +52,7 @@ voltage-tolerance = <1>; /* 1% */ clocks = <&cpg_clocks R8A7790_CLK_Z>; clock-latency = <300000>; /* 300 us */ + next-level-cache = <&L2_CA15>; /* kHz - uV - OPPs unknown yet */ operating-points = <1400000 1000000>, @@ -67,6 +68,7 @@ compatible = "arm,cortex-a15"; reg = <1>; clock-frequency = <1300000000>; + next-level-cache = <&L2_CA15>; }; cpu2: cpu@2 { @@ -74,6 +76,7 @@ compatible = "arm,cortex-a15"; reg = <2>; clock-frequency = <1300000000>; + next-level-cache = <&L2_CA15>; }; cpu3: cpu@3 { @@ -81,6 +84,7 @@ compatible = "arm,cortex-a15"; reg = <3>; clock-frequency = <1300000000>; + next-level-cache = <&L2_CA15>; }; cpu4: cpu@4 { @@ -88,6 +92,7 @@ compatible = "arm,cortex-a7"; reg = <0x100>; clock-frequency = <780000000>; + next-level-cache = <&L2_CA7>; }; cpu5: cpu@5 { @@ -95,6 +100,7 @@ compatible = "arm,cortex-a7"; reg = <0x101>; clock-frequency = <780000000>; + next-level-cache = <&L2_CA7>; }; cpu6: cpu@6 { @@ -102,6 +108,7 @@ compatible = "arm,cortex-a7"; reg = <0x102>; clock-frequency = <780000000>; + next-level-cache = <&L2_CA7>; }; cpu7: cpu@7 { @@ -109,9 +116,24 @@ compatible = "arm,cortex-a7"; reg = <0x103>; clock-frequency = <780000000>; + next-level-cache = <&L2_CA7>; }; }; + L2_CA15: cache-controller@0 { + compatible = "cache"; + arm,data-latency = <4 4 1>; + arm,tag-latency = <3 3 3>; + cache-unified; + cache-level = <2>; + }; + + L2_CA7: cache-controller@1 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + }; + gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; #interrupt-cells = <3>;