| Message ID | 1449512659-16688-7-git-send-email-geert+renesas@glider.be (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Simon Horman |
| Headers | show |
On 07/12/15 18:24, Geert Uytterhoeven wrote: > Add device nodes for the L2 caches, and link the CPU node to its L2 > cache node. > > The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as > 128 KiB x 16 ways), and requires the following settings: > - Tag RAM latency: 3 cycles, > - Data RAM latency: 4 cycles, > - Data RAM setup: 1 cycles, > > The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as > 32 KiB x 16 ways). > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> > --- > What are the DT bindings for Cortex-A57/A53 L2 cache controllers? > There's no special binding specific to cpus. Yes the generic binding should be fine as we don't have to deal with their configuration in the kernel and assumed to be all preconfigured by early secure boot code. > v2: > - New. > --- > arch/arm64/boot/dts/renesas/r8a7795.dtsi | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi > index 816400c1bee604db..30063546c7e9bbea 100644 > --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi > @@ -35,9 +35,24 @@ > compatible = "arm,cortex-a57", "arm,armv8"; > reg = <0x0>; > device_type = "cpu"; > + next-level-cache = <&L2_CA57>; > }; > }; > > + L2_CA57: cache-controller@0 { > + compatible = "cache"; > + arm,data-latency = <4 4 1>; > + arm,tag-latency = <3 3 3>; Interesting, only PL2xx/3xx cache controller driver reads this from the DT and configures the controller. The integrated L2 found in A15/A7/A57/A53 needs doesn't make use of these values from the DT. I assume these values are tested and configured by boot loaders before entering Linux. I am not objecting to their presence here but I am mentioning that it's mostly of no use for Linux as software running at higher EL might not allow these configuration to be modified.
On Mon, Dec 07, 2015 at 06:49:43PM +0000, Sudeep Holla wrote: > > On 07/12/15 18:24, Geert Uytterhoeven wrote: > >+ L2_CA57: cache-controller@0 { > >+ compatible = "cache"; > >+ arm,data-latency = <4 4 1>; > >+ arm,tag-latency = <3 3 3>; > > Interesting, only PL2xx/3xx cache controller driver reads this from the > DT and configures the controller. The integrated L2 found in > A15/A7/A57/A53 needs doesn't make use of these values from the DT. These properties seem to be from l2cc.txt, which really only corresponds to PL210/PL220/PL310 (and variants) and isn't as generic as it sounds. I don't see that these are necessary at all. Thanks, Mark. -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Mark, On Mon, Dec 7, 2015 at 8:03 PM, Mark Rutland <mark.rutland@arm.com> wrote: > On Mon, Dec 07, 2015 at 06:49:43PM +0000, Sudeep Holla wrote: >> On 07/12/15 18:24, Geert Uytterhoeven wrote: >> >+ L2_CA57: cache-controller@0 { >> >+ compatible = "cache"; >> >+ arm,data-latency = <4 4 1>; >> >+ arm,tag-latency = <3 3 3>; >> >> Interesting, only PL2xx/3xx cache controller driver reads this from the >> DT and configures the controller. The integrated L2 found in >> A15/A7/A57/A53 needs doesn't make use of these values from the DT. > > These properties seem to be from l2cc.txt, which really only corresponds > to PL210/PL220/PL310 (and variants) and isn't as generic as it sounds. > > I don't see that these are necessary at all. The datasheet does mention the data/tag RAM latencies/setup values, so I put them in DT using the properties I could fine. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Mark, On Mon, Dec 7, 2015 at 9:18 PM, Geert Uytterhoeven <geert@linux-m68k.org> wrote: > On Mon, Dec 7, 2015 at 8:03 PM, Mark Rutland <mark.rutland@arm.com> wrote: >> On Mon, Dec 07, 2015 at 06:49:43PM +0000, Sudeep Holla wrote: >>> On 07/12/15 18:24, Geert Uytterhoeven wrote: >>> >+ L2_CA57: cache-controller@0 { >>> >+ compatible = "cache"; >>> >+ arm,data-latency = <4 4 1>; >>> >+ arm,tag-latency = <3 3 3>; >>> >>> Interesting, only PL2xx/3xx cache controller driver reads this from the >>> DT and configures the controller. The integrated L2 found in >>> A15/A7/A57/A53 needs doesn't make use of these values from the DT. >> >> These properties seem to be from l2cc.txt, which really only corresponds >> to PL210/PL220/PL310 (and variants) and isn't as generic as it sounds. >> >> I don't see that these are necessary at all. > > The datasheet does mention the data/tag RAM latencies/setup values, so > I put them in DT using the properties I could fine. Furthermore these values are different for different SoCs in the same family (e.g. r8a7790 vs. other R-Car Gen2 members), even though they seem to have the same Cortex-A15 cores. So to me these look like properties we want to document in the DTS... Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 816400c1bee604db..30063546c7e9bbea 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -35,9 +35,24 @@ compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x0>; device_type = "cpu"; + next-level-cache = <&L2_CA57>; }; }; + L2_CA57: cache-controller@0 { + compatible = "cache"; + arm,data-latency = <4 4 1>; + arm,tag-latency = <3 3 3>; + cache-unified; + cache-level = <2>; + }; + + L2_CA53: cache-controller@1 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + }; + extal_clk: extal { compatible = "fixed-clock"; #clock-cells = <0>;
Add device nodes for the L2 caches, and link the CPU node to its L2 cache node. The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as 128 KiB x 16 ways), and requires the following settings: - Tag RAM latency: 3 cycles, - Data RAM latency: 4 cycles, - Data RAM setup: 1 cycles, The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as 32 KiB x 16 ways). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> --- What are the DT bindings for Cortex-A57/A53 L2 cache controllers? v2: - New. --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+)