From patchwork Mon Dec 7 18:24:19 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 7788981 X-Patchwork-Delegate: horms@verge.net.au Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E95E99F1C2 for ; Mon, 7 Dec 2015 18:24:59 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 132E52054B for ; Mon, 7 Dec 2015 18:24:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 343192053D for ; Mon, 7 Dec 2015 18:24:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755844AbbLGSY5 (ORCPT ); Mon, 7 Dec 2015 13:24:57 -0500 Received: from [195.130.137.89] ([195.130.137.89]:43889 "EHLO laurent.telenet-ops.be" rhost-flags-FAIL-FAIL-OK-OK) by vger.kernel.org with ESMTP id S1755008AbbLGSY5 (ORCPT ); Mon, 7 Dec 2015 13:24:57 -0500 Received: from ayla.of.borg ([84.195.106.123]) by laurent.telenet-ops.be with bizsmtp id qiQT1r00P2fm56U01iQTda; Mon, 07 Dec 2015 19:24:35 +0100 Received: from ramsan.of.borg ([192.168.97.29] helo=ramsan) by ayla.of.borg with esmtp (Exim 4.82) (envelope-from ) id 1a60SZ-00036i-20; Mon, 07 Dec 2015 19:24:27 +0100 Received: from geert by ramsan with local (Exim 4.82) (envelope-from ) id 1a60Sa-0004MK-RL; Mon, 07 Dec 2015 19:24:28 +0100 From: Geert Uytterhoeven To: Simon Horman , Magnus Damm Cc: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Catalin Marinas , Will Deacon , Sudeep Holla , Lina Iyer , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-sh@vger.kernel.org, linux-pm@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes Date: Mon, 7 Dec 2015 19:24:19 +0100 Message-Id: <1449512659-16688-7-git-send-email-geert+renesas@glider.be> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1449512659-16688-1-git-send-email-geert+renesas@glider.be> References: <1449512659-16688-1-git-send-email-geert+renesas@glider.be> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add device nodes for the L2 caches, and link the CPU node to its L2 cache node. The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as 128 KiB x 16 ways), and requires the following settings: - Tag RAM latency: 3 cycles, - Data RAM latency: 4 cycles, - Data RAM setup: 1 cycles, The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as 32 KiB x 16 ways). Signed-off-by: Geert Uytterhoeven --- What are the DT bindings for Cortex-A57/A53 L2 cache controllers? v2: - New. --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 816400c1bee604db..30063546c7e9bbea 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -35,9 +35,24 @@ compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x0>; device_type = "cpu"; + next-level-cache = <&L2_CA57>; }; }; + L2_CA57: cache-controller@0 { + compatible = "cache"; + arm,data-latency = <4 4 1>; + arm,tag-latency = <3 3 3>; + cache-unified; + cache-level = <2>; + }; + + L2_CA53: cache-controller@1 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + }; + extal_clk: extal { compatible = "fixed-clock"; #clock-cells = <0>;