From patchwork Sat Dec 12 07:16:46 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dirk Behme X-Patchwork-Id: 7834201 X-Patchwork-Delegate: horms@verge.net.au Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id B00CF9F1C2 for ; Sat, 12 Dec 2015 07:17:12 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B65B62041C for ; Sat, 12 Dec 2015 07:17:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id ACBEA20414 for ; Sat, 12 Dec 2015 07:17:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751005AbbLLHQx (ORCPT ); Sat, 12 Dec 2015 02:16:53 -0500 Received: from mail-wm0-f43.google.com ([74.125.82.43]:37006 "EHLO mail-wm0-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750798AbbLLHQx (ORCPT ); Sat, 12 Dec 2015 02:16:53 -0500 Received: by wmnn186 with SMTP id n186so59279015wmn.0; Fri, 11 Dec 2015 23:16:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=FSB/5vkaMWpdohnGR+q/JhTEFo4Sfv++HrbDaryDujo=; b=KQC8FszamoWCZudUtOUv0OIww7BBAYuLV28DzgdDg+jJWFuh2YRFG8r2lx65TAT/15 ucWOlPMQxQWY4CNq611MMAdG3D+bldtgRrh37XgSS0VVXp0S2FeG4qQZPKJN7AmYM8r9 oyFJXVoVYKsCj93NYqgwFpHdp1xfEV4v+oSeEPKXZVTh0XgqIVjyBkwtMVhlR1UT+T0a yKPktki4f0CBOcbXtG9ZODphSjUYJia8umAbkPGJy6l8lSua5BhF/tIDGhSnRCpz1hTc IC3PB2VYcifKHzvhQeY1kX/Yj20uPj1Cor0C9G9+FgKPPJPJdzimiP4RdfuQFY6Tf48s 5q3Q== X-Received: by 10.194.82.99 with SMTP id h3mr28139154wjy.41.1449904611520; Fri, 11 Dec 2015 23:16:51 -0800 (PST) Received: from localhost.localdomain (p4FEE252A.dip0.t-ipconnect.de. [79.238.37.42]) by smtp.gmail.com with ESMTPSA id gl10sm20020317wjb.30.2015.12.11.23.16.49 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 11 Dec 2015 23:16:50 -0800 (PST) From: Dirk Behme To: linux-sh@vger.kernel.org, horms@verge.net.au, geert+renesas@glider.be Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Takeshi Kihara , Dirk Behme Subject: [PATCH 1/2] arm64: dts: r8a7795: Add Cortex-A53 CPU cores Date: Sat, 12 Dec 2015 08:16:46 +0100 Message-Id: <1449904607-4060-1-git-send-email-dirk.behme@gmail.com> X-Mailer: git-send-email 2.6.4 Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Takeshi Kihara This patch adds Cortex-A53 CPU cores to r8a7795 SoC for a total of 8 cores (4 x Cortex-A57 + 4 x Cortex-A53). Signed-off-by: Takeshi Kihara Signed-off-by: Dirk Behme --- Note: This patch is picked from https://git.kernel.org/cgit/linux/kernel/git/horms/renesas-bsp.git/log/?h=v4.2/rcar-3.0.x and rebased against https://git.kernel.org/cgit/linux/kernel/git/horms/renesas.git/log/?h=next renesas-next-20151211v2-v4.4-rc1 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 46 +++++++++++++++++++++++++++----- 1 file changed, 39 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index b9229a4..3633a2a 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -60,6 +60,30 @@ device_type = "cpu"; enable-method = "psci"; }; + a53_0: cpu@100 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x100>; + device_type = "cpu"; + enable-method = "psci"; + }; + a53_1: cpu@101 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x101>; + device_type = "cpu"; + enable-method = "psci"; + }; + a53_2: cpu@102 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x102>; + device_type = "cpu"; + enable-method = "psci"; + }; + a53_3: cpu@103 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x103>; + device_type = "cpu"; + enable-method = "psci"; + }; }; extal_clk: extal { @@ -115,7 +139,7 @@ reg = <0x0 0xf1010000 0 0x1000>, <0x0 0xf1020000 0 0x2000>; interrupts = ; + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; }; gpio0: gpio@e6050000 { @@ -235,23 +259,31 @@ interrupts = , , , - ; + , + , + , + , + ; interrupt-affinity = <&a57_0>, <&a57_1>, <&a57_2>, - <&a57_3>; + <&a57_3>, + <&a53_0>, + <&a53_1>, + <&a53_2>, + <&a53_3>; }; timer { compatible = "arm,armv8-timer"; interrupts = , + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, , + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, , + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, ; + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; }; cpg: clock-controller@e6150000 {