From patchwork Thu Dec 17 13:22:35 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Phil Edworthy X-Patchwork-Id: 7873251 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 41DB99F54F for ; Thu, 17 Dec 2015 13:24:16 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2EC8F20412 for ; Thu, 17 Dec 2015 13:24:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4ACB920421 for ; Thu, 17 Dec 2015 13:24:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755243AbbLQNXU (ORCPT ); Thu, 17 Dec 2015 08:23:20 -0500 Received: from relmlor3.renesas.com ([210.160.252.173]:37276 "EHLO relmlie2.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S966642AbbLQNXR (ORCPT ); Thu, 17 Dec 2015 08:23:17 -0500 Received: from unknown (HELO relmlir1.idc.renesas.com) ([10.200.68.151]) by relmlie2.idc.renesas.com with ESMTP; 17 Dec 2015 22:23:14 +0900 Received: from relmlac4.idc.renesas.com (relmlac4.idc.renesas.com [10.200.69.24]) by relmlir1.idc.renesas.com (Postfix) with ESMTP id 0BF2E40D0F; Thu, 17 Dec 2015 22:23:15 +0900 (JST) Received: by relmlac4.idc.renesas.com (Postfix, from userid 0) id ED0AE480A3; Thu, 17 Dec 2015 22:23:14 +0900 (JST) Received: from relmlac4.idc.renesas.com (localhost [127.0.0.1]) by relmlac4.idc.renesas.com (Postfix) with ESMTP id E77B348014; Thu, 17 Dec 2015 22:23:14 +0900 (JST) Received: from relmlii1.idc.renesas.com [10.200.68.65] by relmlac4.idc.renesas.com with ESMTP id YBL03715; Thu, 17 Dec 2015 22:23:14 +0900 X-IronPort-AV: E=Sophos;i="5.20,441,1444662000"; d="scan'208";a="200776548" Received: from unknown (HELO localhost.localdomain) ([172.29.43.47]) by relmlii1.idc.renesas.com with ESMTP; 17 Dec 2015 22:23:12 +0900 From: Phil Edworthy To: Simon Horman , Bjorn Helgaas Cc: Wolfram Sang , Geert Uytterhoeven , , , , Phil Edworthy Subject: [PATCH 2/4] PCI: rcar: Support runtime PM link state L1 handling in pcie-rcar Date: Thu, 17 Dec 2015 13:22:35 +0000 Message-Id: <1450358557-28376-3-git-send-email-phil.edworthy@renesas.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1450358557-28376-1-git-send-email-phil.edworthy@renesas.com> References: <1450358557-28376-1-git-send-email-phil.edworthy@renesas.com> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The R-Car PCIe host controller does not handle L1 ASPM. Instead, the hardware needs assistance to transition to L1. When the controller has received a PM_ENTER_L1 DLLP, we can't access a card's config regs until we have got it out of L1 link state. The host controller will handle this as long as it has also been transitioned to L1 link state. So, when attempting a config access, check to see if the card has gone into L1, and if so, do the same for the host controller. This is based on a patch by Hien Dang Signed-off-by: Phil Edworthy --- drivers/pci/host/pcie-rcar.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/host/pcie-rcar.c index c72c0ae..4a4f8e1 100644 --- a/drivers/pci/host/pcie-rcar.c +++ b/drivers/pci/host/pcie-rcar.c @@ -83,6 +83,14 @@ #define MACSR 0x011054 #define MACCTLR 0x011058 #define SCRAMBLE_DISABLE (1 << 27) +#define PMSR 0x01105c +#define L1FAEG (1 << 31) +#define PM_ENTER_L1RX (1 << 23) +#define PMSTATE (7 << 16) +#define PMSTATE_L1 (3 << 16) +#define PMCTLR 0x011060 +#define L1_INIT (1 << 31) + /* R-Car H1 PHY */ #define H1_PCIEPHYADRR 0x04000c @@ -175,6 +183,7 @@ static int rcar_pcie_config_access(struct rcar_pcie *pcie, unsigned int devfn, int where, u32 *data) { int dev, func, reg, index; + u32 val; dev = PCI_SLOT(devfn); func = PCI_FUNC(devfn); @@ -216,6 +225,22 @@ static int rcar_pcie_config_access(struct rcar_pcie *pcie, if (pcie->root_bus_nr < 0) return PCIBIOS_DEVICE_NOT_FOUND; + /* + * If we are not in L1 link state but have received PM_ENTER_L1 DLLP, + * transition to L1 link state. The HW will handle coming out of L1. + */ + val = rcar_pci_read_reg(pcie, PMSR); + if ((val & PM_ENTER_L1RX) && ((val & PMSTATE) != PMSTATE_L1)) { + rcar_pci_write_reg(pcie, L1_INIT, PMCTLR); + + /* Wait until we are in L1 */ + while (!(val & L1FAEG)) + val = rcar_pci_read_reg(pcie, PMSR); + + /* Clear flags indicating link has transitioned to L1 */ + rcar_pci_write_reg(pcie, L1FAEG | PM_ENTER_L1RX, PMSR); + } + /* Clear errors */ rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR);