From patchwork Fri Apr 29 12:58:30 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 8981261 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id B3D319F54E for ; Fri, 29 Apr 2016 13:01:03 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C30382017E for ; Fri, 29 Apr 2016 13:01:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E4C9F20166 for ; Fri, 29 Apr 2016 13:01:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753405AbcD2M7a (ORCPT ); Fri, 29 Apr 2016 08:59:30 -0400 Received: from albert.telenet-ops.be ([195.130.137.90]:50097 "EHLO albert.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753865AbcD2M6w (ORCPT ); Fri, 29 Apr 2016 08:58:52 -0400 Received: from ayla.of.borg ([84.195.109.243]) by albert.telenet-ops.be with bizsmtp id oCyj1s0155F7gFG06CyjVR; Fri, 29 Apr 2016 14:58:46 +0200 Received: from ramsan.of.borg ([192.168.97.29] helo=ramsan) by ayla.of.borg with esmtp (Exim 4.82) (envelope-from ) id 1aw80J-00025I-RH; Fri, 29 Apr 2016 14:58:43 +0200 Received: from geert by ramsan with local (Exim 4.82) (envelope-from ) id 1aw80L-0004sd-GK; Fri, 29 Apr 2016 14:58:45 +0200 From: Geert Uytterhoeven To: Greg Kroah-Hartman , Jiri Slaby , Peter Hurley Cc: Magnus Damm , Laurent Pinchart , Yoshinori Sato , linux-serial@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-sh@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 07/11] serial: sh-sci: Add more Serial Port Control/Data Register documentation Date: Fri, 29 Apr 2016 14:58:30 +0200 Message-Id: <1461934714-18681-8-git-send-email-geert+renesas@glider.be> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1461934714-18681-1-git-send-email-geert+renesas@glider.be> References: <1461934714-18681-1-git-send-email-geert+renesas@glider.be> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Improve documentation for the SCIFA/SCIFB Serial Port Control and Data Registers: - State clearly that the RTS and CTS lines are active-low, - Document the bits related to the serial port's SCK, RXD, and TXD pins. Signed-off-by: Geert Uytterhoeven Reviewed-by: Peter Hurley --- v2: - New. --- drivers/tty/serial/sh-sci.h | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/tty/serial/sh-sci.h b/drivers/tty/serial/sh-sci.h index 85a2b81ba0a845e5..e7d2bc692a581e9e 100644 --- a/drivers/tty/serial/sh-sci.h +++ b/drivers/tty/serial/sh-sci.h @@ -121,12 +121,18 @@ enum { #define HSCIF_SRE BIT(15) /* Sampling Rate Register Enable */ /* SCPCR (Serial Port Control Register), SCIFA/SCIFB only */ -#define SCPCR_RTSC BIT(4) /* Serial Port RTS Pin / Output Pin */ -#define SCPCR_CTSC BIT(3) /* Serial Port CTS Pin / Input Pin */ +#define SCPCR_RTSC BIT(4) /* Serial Port RTS# Pin / Output Pin */ +#define SCPCR_CTSC BIT(3) /* Serial Port CTS# Pin / Input Pin */ +#define SCPCR_SCKC BIT(2) /* Serial Port SCK Pin / Output Pin */ +#define SCPCR_RXDC BIT(1) /* Serial Port RXD Pin / Input Pin */ +#define SCPCR_TXDC BIT(0) /* Serial Port TXD Pin / Output Pin */ /* SCPDR (Serial Port Data Register), SCIFA/SCIFB only */ -#define SCPDR_RTSD BIT(4) /* Serial Port RTS Output Pin Data */ -#define SCPDR_CTSD BIT(3) /* Serial Port CTS Input Pin Data */ +#define SCPDR_RTSD BIT(4) /* Serial Port RTS# Output Pin Data */ +#define SCPDR_CTSD BIT(3) /* Serial Port CTS# Input Pin Data */ +#define SCPDR_SCKD BIT(2) /* Serial Port SCK Output Pin Data */ +#define SCPDR_RXDD BIT(1) /* Serial Port RXD Input Pin Data */ +#define SCPDR_TXDD BIT(0) /* Serial Port TXD Output Pin Data */ /* * BRG Clock Select Register (Some SCIF and HSCIF)