From patchwork Sun May 1 05:08:33 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 8988101 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 2F673BF29F for ; Sun, 1 May 2016 05:12:09 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 322C0202EB for ; Sun, 1 May 2016 05:12:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F0ED7202F8 for ; Sun, 1 May 2016 05:12:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752195AbcEAFIu (ORCPT ); Sun, 1 May 2016 01:08:50 -0400 Received: from mail2.asahi-net.or.jp ([202.224.39.198]:55800 "EHLO mail2.asahi-net.or.jp" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751399AbcEAFIn (ORCPT ); Sun, 1 May 2016 01:08:43 -0400 Received: from sa76r4 (y081184.ppp.asahi-net.or.jp [118.243.81.184]) by mail2.asahi-net.or.jp (Postfix) with ESMTP id 7278AFDA5; Sun, 1 May 2016 14:08:41 +0900 (JST) Received: from localhost (localhost [127.0.0.1]) by sa76r4 (Postfix) with ESMTP id 556BD1214E; Sun, 1 May 2016 14:08:41 +0900 (JST) X-Virus-Scanned: Debian amavisd-new at sa76r4.localdomain Received: from sa76r4 ([127.0.0.1]) by localhost (sa76r4.localdomain [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id VbdTM4w2X2W3; Sun, 1 May 2016 14:08:41 +0900 (JST) Received: by sa76r4 (Postfix, from userid 1000) id EFA6511D3B; Sun, 1 May 2016 14:08:40 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Yoshinori Sato Subject: [PATCH RESEND 09/12] sh: Add I/O DATA HDL-U support drivers. Date: Sun, 1 May 2016 14:08:33 +0900 Message-Id: <1462079316-27771-10-git-send-email-ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1462079316-27771-1-git-send-email-ysato@users.sourceforge.jp> References: <1462079316-27771-1-git-send-email-ysato@users.sourceforge.jp> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP PCI host fixup and external interrupt controller. Signed-off-by: Yoshinori Sato --- .../interrupt-controller/iodata-landisk.txt | 28 +++++++++ drivers/irqchip/irq-io-landisk.c | 71 ++++++++++++++++++++++ drivers/pci/host/pci-sh7751.c | 25 ++++++++ 3 files changed, 124 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/iodata-landisk.txt create mode 100644 drivers/irqchip/irq-io-landisk.c diff --git a/Documentation/devicetree/bindings/interrupt-controller/iodata-landisk.txt b/Documentation/devicetree/bindings/interrupt-controller/iodata-landisk.txt new file mode 100644 index 0000000..09c2841 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/iodata-landisk.txt @@ -0,0 +1,28 @@ +DT bindings for the I/O DATA HDL-U interrupt controler + +Required properties: + + - compatible: has to be "iodata,landisk-intc". + + - reg: Base address and length of interrupt controller register. + + - interrupt-controller: Identifies the node as an interrupt controller. + + - #interrupt-cells: has to be <2>: an interrupt index and flags, as defined + in interrupts.txt in this directory. + + - interrupt-map: Interrupt mapping on parent controler. + +Example +------- + + cpldintc: cpld@b0000000 { + compatible = "iodata,landisk-intc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xb0000000 8>; + interrupt-map=<0 &shintc 0 0>, <1 &shintc 1 0>, + <2 &shintc 2 0>, <3 &shintc 3 0>, + <4 &shintc 4 0>, <5 &shintc 5 0>, + <6 &shintc 6 0>, <7 &shintc 7 0>; + }; diff --git a/drivers/irqchip/irq-io-landisk.c b/drivers/irqchip/irq-io-landisk.c new file mode 100644 index 0000000..c351925 --- /dev/null +++ b/drivers/irqchip/irq-io-landisk.c @@ -0,0 +1,71 @@ +/* + * IO-DATA LANDISK CPLD IRQ driver + * + * Copyright 2016 Yoshinori Sato + */ + +#include +#include +#include +#include +#include +#include +#include + +static void landisk_mask_irq(struct irq_data *data) +{ + u8 mask = __raw_readb(data->chip_data + 5); + + mask &= !(1 << (data->irq - 5)); + __raw_writeb(mask, data->chip_data + 5); +} + +static void landisk_unmask_irq(struct irq_data *data) +{ + u8 mask = __raw_readb(data->chip_data + 5); + + mask |= (1 << (data->irq - 5)); + __raw_writeb(mask, data->chip_data + 5); +} + +static struct irq_chip cpld_irq_chip = { + .name = "LANDISK-CPLD", + .irq_unmask = landisk_unmask_irq, + .irq_mask = landisk_mask_irq, +}; + +static int cpld_map(struct irq_domain *d, unsigned int virq, + irq_hw_number_t hw_irq_num) +{ + irq_set_chip_and_handler(virq, &cpld_irq_chip, + handle_simple_irq); + irq_set_chip_data(virq, d->host_data); + + return 0; +} + +static struct irq_domain_ops irq_ops = { + .xlate = irq_domain_xlate_twocell, + .map = cpld_map, +}; + +static int __init landisk_intc_of_init(struct device_node *intc, + struct device_node *parent) +{ + struct irq_domain *domain, *pdomain; + int num_irqpin; + void *baseaddr; + + baseaddr = of_iomap(intc, 0); + pdomain = irq_find_host(parent); + of_get_property(intc, "interrupt-map", &num_irqpin); + num_irqpin /= sizeof(u32) * 3; + domain = irq_domain_create_hierarchy(pdomain, 0, num_irqpin, + of_node_to_fwnode(intc), + &irq_ops, baseaddr); + BUG_ON(!domain); + irq_domain_associate_many(domain, 0, 0, 8); + return 0; +} + +IRQCHIP_DECLARE(cpld_intc, "iodata,landisk-intc", landisk_intc_of_init); diff --git a/drivers/pci/host/pci-sh7751.c b/drivers/pci/host/pci-sh7751.c index fd6548b..3fa0da5 100644 --- a/drivers/pci/host/pci-sh7751.c +++ b/drivers/pci/host/pci-sh7751.c @@ -26,10 +26,35 @@ DEFINE_RAW_SPINLOCK(pci_config_lock); * PCIC fixups */ +#define PCIMCR_MRSET 0x40000000 +#define PCIMCR_RFSH 0x00000004 + +static void __init landisk_fixup(void __iomem *pci_reg_base, void __iomem *bcr) +{ + unsigned long bcr1, mcr; + + bcr1 = __raw_readl(bcr + SH7751_BCR1); + bcr1 |= 0x00080000; /* Enable Bit 19 BREQEN, set PCIC to slave */ + pcic_writel(bcr1, SH4_PCIBCR1); + + mcr = __raw_readl(bcr + SH7751_MCR); + mcr &= (~PCIMCR_MRSET) & (~PCIMCR_RFSH); + pcic_writel(mcr, SH4_PCIMCR); + + pcic_writel(0x0c000000, SH7751_PCICONF5); + pcic_writel(0xd0000000, SH7751_PCICONF6); + pcic_writel(0x0c000000, SH4_PCILAR0); + pcic_writel(0x00000000, SH4_PCILAR1); +} + static __initconst const struct fixups { char *compatible; void (*fixup)(void __iomem *, void __iomem *); } fixup_list[] = { + { + .compatible = "iodata,landisk", + .fixup = landisk_fixup, + }, }; static __init void pcic_fixups(struct device_node *np,