From patchwork Thu May 28 12:00:25 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Magnus Damm X-Patchwork-Id: 26724 Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n4SC3dL6008751 for ; Thu, 28 May 2009 12:03:39 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759081AbZE1MDg (ORCPT ); Thu, 28 May 2009 08:03:36 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1759030AbZE1MDg (ORCPT ); Thu, 28 May 2009 08:03:36 -0400 Received: from rv-out-0506.google.com ([209.85.198.231]:16842 "EHLO rv-out-0506.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758938AbZE1MDf (ORCPT ); Thu, 28 May 2009 08:03:35 -0400 Received: by rv-out-0506.google.com with SMTP id f9so1647573rvb.1 for ; Thu, 28 May 2009 05:03:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:date:message-id :subject; bh=20AlgDpue1OksOYw7eKXx8xtK7OfpquTFF/Sx+ae5bQ=; b=bLvbKCI5F+xQEbfQpyZOfmCbPP7A7A46bWX9eqkSdxMbXVkJKL5MnR/9gXkhOfzVsz k3kIvMWU0prrp7D8okOlLSl579GM3Trsm9DgoYNcL57x7PwOyPOnvvdyq70zW2oyCFlK yt4XJZTkSMofaGIJIjN+nthUuyHxXaIJYnhBw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:date:message-id:subject; b=WVS4Bro6l7tONkUp2raoHiKErEQk+g4zOika8IwxV8/HctCVzeaYPy0edDN49SmFjr yqQoF/TMeCwZnHHcswoaDg+2I5DeEPKWRsmMjglT2flQ2NZvil4FddRnOg/WGiZe181N PN7LGjjVl6JrWjUpNrboti9h1dreN4CZI3Q6k= Received: by 10.141.21.5 with SMTP id y5mr628307rvi.178.1243512215505; Thu, 28 May 2009 05:03:35 -0700 (PDT) Received: from rx1.opensource.se (210.5.32.202.bf.2iij.net [202.32.5.210]) by mx.google.com with ESMTPS id g22sm28107946rvb.56.2009.05.28.05.03.34 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 28 May 2009 05:03:35 -0700 (PDT) From: Magnus Damm To: linux-sh@vger.kernel.org Cc: Magnus Damm , lethal@linux-sh.org Date: Thu, 28 May 2009 21:00:25 +0900 Message-Id: <20090528120025.5834.4382.sendpatchset@rx1.opensource.se> Subject: [PATCH] sh: sh7785lcr mode pin configuration Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org From: Magnus Damm This patch adds mode pin support to the sh7785lcr board. The harware allows the user to control the mode pins using dip switches S1 and S2, but from the software the pins are fixed to the factory default since we have no way to reading out this configuration from software. Signed-off-by: Magnus Damm --- arch/sh/boards/board-sh7785lcr.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html --- 0001/arch/sh/boards/board-sh7785lcr.c +++ work/arch/sh/boards/board-sh7785lcr.c 2009-05-28 18:48:03.000000000 +0900 @@ -24,6 +24,7 @@ #include #include #include +#include /* * NOTE: This board has 2 physical memory maps. @@ -320,6 +321,26 @@ static void __init sh7785lcr_setup(char writel(0x000307c2, sm501_reg); } +/* Return the board specific boot mode pin configuration */ +static int sh7785lcr_mode_pins(void) +{ + int value = 0; + + /* These are the factory default settings of S1 and S2. + * If you change these dip switches then you will need to + * adjust the values below as well. + */ + value |= 1 << MODE_PIN_MODE4; /* Clock Mode 16 */ + value |= 1 << MODE_PIN_MODE5; /* 32-bit Area0 bus width */ + value |= 1 << MODE_PIN_MODE6; /* 32-bit Area0 bus width */ + value |= 1 << MODE_PIN_MODE7; /* Area 0 SRAM interface [fixed] */ + value |= 1 << MODE_PIN_MODE8; /* Little Endian */ + value |= 1 << MODE_PIN_MODE9; /* Master Mode */ + value |= 1 << MODE_PIN_MODE14; /* No PLL step-up */ + + return value; +} + /* * The Machine Vector */ @@ -328,5 +349,6 @@ static struct sh_machine_vector mv_sh778 .mv_setup = sh7785lcr_setup, .mv_clk_init = sh7785lcr_clk_init, .mv_init_irq = init_sh7785lcr_IRQ, + .mv_mode_pins = sh7785lcr_mode_pins, };