From patchwork Thu Nov 5 05:02:09 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Mundt X-Patchwork-Id: 57826 Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id nA552ai2027020 for ; Thu, 5 Nov 2009 05:02:36 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750787AbZKEFC3 (ORCPT ); Thu, 5 Nov 2009 00:02:29 -0500 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1750792AbZKEFC3 (ORCPT ); Thu, 5 Nov 2009 00:02:29 -0500 Received: from 124x34x33x190.ap124.ftth.ucom.ne.jp ([124.34.33.190]:38728 "EHLO master.linux-sh.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750787AbZKEFC3 (ORCPT ); Thu, 5 Nov 2009 00:02:29 -0500 Received: from localhost (unknown [127.0.0.1]) by master.linux-sh.org (Postfix) with ESMTP id 2C98663758; Thu, 5 Nov 2009 05:02:13 +0000 (UTC) X-Virus-Scanned: amavisd-new at linux-sh.org Received: from master.linux-sh.org ([127.0.0.1]) by localhost (master.linux-sh.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Iu+AtBzyNrF9; Thu, 5 Nov 2009 14:02:09 +0900 (JST) Received: by master.linux-sh.org (Postfix, from userid 500) id 0EDDF6375A; Thu, 5 Nov 2009 14:02:09 +0900 (JST) Date: Thu, 5 Nov 2009 14:02:09 +0900 From: Paul Mundt To: Kuninori Morimoto Cc: SH-Linux , Magnus Subject: Re: [PATCH] sh: mach-ecovec24: Enable SPU2 clock when boot Message-ID: <20091105050208.GB26910@linux-sh.org> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.13 (2006-08-11) Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c index dfe9192..9db7438 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c @@ -152,7 +152,7 @@ struct clk div6_clks[] = { SH_CLK_DIV6("fsia_clk", &div3_clk, FCLKACR, 0), SH_CLK_DIV6("fsib_clk", &div3_clk, FCLKBCR, 0), SH_CLK_DIV6("irda_clk", &div3_clk, IRDACLKCR, 0), - SH_CLK_DIV6("spu_clk", &div3_clk, SPUCLKCR, 0), + SH_CLK_DIV6("spu_clk", &div3_clk, SPUCLKCR, CLK_ENABLE_ON_INIT), }; #define R_CLK (&r_clk)