From patchwork Tue Feb 9 03:35:42 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Magnus Damm X-Patchwork-Id: 77928 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o193gEoP013834 for ; Tue, 9 Feb 2010 03:42:25 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753346Ab0BIDmZ (ORCPT ); Mon, 8 Feb 2010 22:42:25 -0500 Received: from mail-yw0-f189.google.com ([209.85.211.189]:53453 "EHLO mail-yw0-f189.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752361Ab0BIDmY (ORCPT ); Mon, 8 Feb 2010 22:42:24 -0500 Received: by mail-yw0-f189.google.com with SMTP id 27so6144036ywh.1 for ; Mon, 08 Feb 2010 19:42:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:date:message-id :in-reply-to:references:subject; bh=5qDdRPaqfyyRKOOJ4+uGQCOkiIu1Zq09cO0oHE29t14=; b=jzTG8vcr7PVCmYOHAOyvEnI9bIDMvAgHK36VjWnTSJ8i6BGAVMppqYau3r3k5HaLSy zMpAhl3/+VLzWgeUS54fS36aTPFTKfSe+kRv4F8FhazSuqbWFGIVbDlWVomdneZ+tjY1 aZtkSGTW60pVtYJcM3IzbyV6lDQvyGyBpHwz8= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:date:message-id:in-reply-to:references:subject; b=vHT305t8qJ8uzYWQOg1OX7Z+TLCoCSClYWJB0ZLp1eGzA7hUpPCiZ6B/De49PiYH8i rhrFTnkwvUzemk7Gi1wM45VN1ZEsSFGTmeLlj7VJ4o2hnRluzHJEi08to+nlPzQtFvuo /J2XsBLJrCzQkfxkfUgHF8rI71tR6b0RJIp4o= Received: by 10.101.132.39 with SMTP id j39mr9601594ann.103.1265686943041; Mon, 08 Feb 2010 19:42:23 -0800 (PST) Received: from rxone.opensource.se (49.14.32.202.bf.2iij.net [202.32.14.49]) by mx.google.com with ESMTPS id 8sm1653114yxg.42.2010.02.08.19.42.19 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 08 Feb 2010 19:42:20 -0800 (PST) From: Magnus Damm To: linux-sh@vger.kernel.org Cc: Magnus Damm , lethal@linux-sh.org Date: Tue, 09 Feb 2010 12:35:42 +0900 Message-Id: <20100209033542.22732.97504.sendpatchset@rxone.opensource.se> In-Reply-To: <20100209033533.22732.2030.sendpatchset@rxone.opensource.se> References: <20100209033533.22732.2030.sendpatchset@rxone.opensource.se> Subject: [PATCH 01/03] ARM: mach-shmobile: sh7367 INTCA support Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 09 Feb 2010 03:42:25 +0000 (UTC) --- 0012/arch/arm/mach-shmobile/Makefile +++ work/arch/arm/mach-shmobile/Makefile 2010-02-08 13:44:08.000000000 +0900 @@ -6,7 +6,7 @@ obj-y := timer.o console.o # CPU objects -obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o +obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o intc-sh7367.o obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7367.o obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7367.o --- /dev/null +++ work/arch/arm/mach-shmobile/intc-sh7367.c 2010-02-08 14:21:21.000000000 +0900 @@ -0,0 +1,270 @@ +/* + * sh7367 processor support - INTC hardware block + * + * Copyright (C) 2010 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include + +enum { + UNUSED_INTCA = 0, + + /* interrupt sources INTCA */ + IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A, + IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A, + DIRC, + CRYPT1_ERR, CRYPT2_STD, + IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1, + ARM11_IRQPMU, ARM11_COMMTX, ARM11_COMMRX, + ETM11_ACQCMP, ETM11_FULL, + MFI_MFIM, MFI_MFIS, + BBIF1, BBIF2, + USBDMAC_USHDMI, + USBHS_USHI0, USBHS_USHI1, + CMT1_CMT10, CMT1_CMT11, CMT1_CMT12, CMT1_CMT13, CMT2, CMT3, + KEYSC_KEY, + SCIFA0, SCIFA1, SCIFA2, SCIFA3, + MSIOF2, MSIOF1, + SCIFA4, SCIFA5, SCIFB, + FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, + SDHI0_SDHI0I0, SDHI0_SDHI0I1, SDHI0_SDHI0I2, SDHI0_SDHI0I3, + SDHI1_SDHI1I0, SDHI1_SDHI1I1, SDHI1_SDHI1I2, SDHI1_SDHI1I3, + MSU_MSU, MSU_MSU2, + IREM, + SIU, + SPU, + IRDA, + TPU0, TPU1, TPU2, TPU3, TPU4, + LCRC, + PINT1, PINT2, + TTI20, + MISTY, + DDM, + SDHI2_SDHI2I0, SDHI2_SDHI2I1, SDHI2_SDHI2I2, SDHI2_SDHI2I3, + RWDT0, RWDT1, + DMAC_1_DEI0, DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3, + DMAC_2_DEI4, DMAC_2_DEI5, DMAC_2_DADERR, + DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3, + DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR, + DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3, + DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR, + + /* interrupt groups INTCA */ + DMAC_1, DMAC_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, + ETM11, ARM11, USBHS, FLCTL, IIC1, SDHI0, SDHI1, SDHI2, +}; + +static struct intc_vect intca_vectors[] = { + INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220), + INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260), + INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0), + INTC_VECT(IRQ6A, 0x02c0), INTC_VECT(IRQ7A, 0x02e0), + INTC_VECT(IRQ8A, 0x0300), INTC_VECT(IRQ9A, 0x0320), + INTC_VECT(IRQ10A, 0x0340), INTC_VECT(IRQ11A, 0x0360), + INTC_VECT(IRQ12A, 0x0380), INTC_VECT(IRQ13A, 0x03a0), + INTC_VECT(IRQ14A, 0x03c0), INTC_VECT(IRQ15A, 0x03e0), + INTC_VECT(DIRC, 0x0560), + INTC_VECT(CRYPT1_ERR, 0x05e0), + INTC_VECT(CRYPT2_STD, 0x0700), + INTC_VECT(IIC1_ALI1, 0x0780), INTC_VECT(IIC1_TACKI1, 0x07a0), + INTC_VECT(IIC1_WAITI1, 0x07c0), INTC_VECT(IIC1_DTEI1, 0x07e0), + INTC_VECT(ARM11_IRQPMU, 0x0800), INTC_VECT(ARM11_COMMTX, 0x0840), + INTC_VECT(ARM11_COMMRX, 0x0860), + INTC_VECT(ETM11_ACQCMP, 0x0880), INTC_VECT(ETM11_FULL, 0x08a0), + INTC_VECT(MFI_MFIM, 0x0900), INTC_VECT(MFI_MFIS, 0x0920), + INTC_VECT(BBIF1, 0x0940), INTC_VECT(BBIF2, 0x0960), + INTC_VECT(USBDMAC_USHDMI, 0x0a00), + INTC_VECT(USBHS_USHI0, 0x0a20), INTC_VECT(USBHS_USHI1, 0x0a40), + INTC_VECT(CMT1_CMT10, 0x0b00), INTC_VECT(CMT1_CMT11, 0x0b20), + INTC_VECT(CMT1_CMT12, 0x0b40), INTC_VECT(CMT1_CMT13, 0x0b60), + INTC_VECT(CMT2, 0x0b80), INTC_VECT(CMT3, 0x0ba0), + INTC_VECT(KEYSC_KEY, 0x0be0), + INTC_VECT(SCIFA0, 0x0c00), INTC_VECT(SCIFA1, 0x0c20), + INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60), + INTC_VECT(MSIOF2, 0x0c80), INTC_VECT(MSIOF1, 0x0d00), + INTC_VECT(SCIFA4, 0x0d20), INTC_VECT(SCIFA5, 0x0d40), + INTC_VECT(SCIFB, 0x0d60), + INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0), + INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0), + INTC_VECT(SDHI0_SDHI0I0, 0x0e00), INTC_VECT(SDHI0_SDHI0I1, 0x0e20), + INTC_VECT(SDHI0_SDHI0I2, 0x0e40), INTC_VECT(SDHI0_SDHI0I3, 0x0e60), + INTC_VECT(SDHI1_SDHI1I0, 0x0e80), INTC_VECT(SDHI1_SDHI1I1, 0x0ea0), + INTC_VECT(SDHI1_SDHI1I2, 0x0ec0), INTC_VECT(SDHI1_SDHI1I3, 0x0ee0), + INTC_VECT(MSU_MSU, 0x0f20), INTC_VECT(MSU_MSU2, 0x0f40), + INTC_VECT(IREM, 0x0f60), + INTC_VECT(SIU, 0x0fa0), + INTC_VECT(SPU, 0x0fc0), + INTC_VECT(IRDA, 0x0480), + INTC_VECT(TPU0, 0x04a0), INTC_VECT(TPU1, 0x04c0), + INTC_VECT(TPU2, 0x04e0), INTC_VECT(TPU3, 0x0500), + INTC_VECT(TPU4, 0x0520), + INTC_VECT(LCRC, 0x0540), + INTC_VECT(PINT1, 0x1000), INTC_VECT(PINT2, 0x1020), + INTC_VECT(TTI20, 0x1100), + INTC_VECT(MISTY, 0x1120), + INTC_VECT(DDM, 0x1140), + INTC_VECT(SDHI2_SDHI2I0, 0x1200), INTC_VECT(SDHI2_SDHI2I1, 0x1220), + INTC_VECT(SDHI2_SDHI2I2, 0x1240), INTC_VECT(SDHI2_SDHI2I3, 0x1260), + INTC_VECT(RWDT0, 0x1280), INTC_VECT(RWDT1, 0x12a0), + INTC_VECT(DMAC_1_DEI0, 0x2000), INTC_VECT(DMAC_1_DEI1, 0x2020), + INTC_VECT(DMAC_1_DEI2, 0x2040), INTC_VECT(DMAC_1_DEI3, 0x2060), + INTC_VECT(DMAC_2_DEI4, 0x2080), INTC_VECT(DMAC_2_DEI5, 0x20a0), + INTC_VECT(DMAC_2_DADERR, 0x20c0), + INTC_VECT(DMAC2_1_DEI0, 0x2100), INTC_VECT(DMAC2_1_DEI1, 0x2120), + INTC_VECT(DMAC2_1_DEI2, 0x2140), INTC_VECT(DMAC2_1_DEI3, 0x2160), + INTC_VECT(DMAC2_2_DEI4, 0x2180), INTC_VECT(DMAC2_2_DEI5, 0x21a0), + INTC_VECT(DMAC2_2_DADERR, 0x21c0), + INTC_VECT(DMAC3_1_DEI0, 0x2200), INTC_VECT(DMAC3_1_DEI1, 0x2220), + INTC_VECT(DMAC3_1_DEI2, 0x2240), INTC_VECT(DMAC3_1_DEI3, 0x2260), + INTC_VECT(DMAC3_2_DEI4, 0x2280), INTC_VECT(DMAC3_2_DEI5, 0x22a0), + INTC_VECT(DMAC3_2_DADERR, 0x22c0), +}; + +static struct intc_group intca_groups[] __initdata = { + INTC_GROUP(DMAC_1, DMAC_1_DEI0, + DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3), + INTC_GROUP(DMAC_2, DMAC_2_DEI4, + DMAC_2_DEI5, DMAC_2_DADERR), + INTC_GROUP(DMAC2_1, DMAC2_1_DEI0, + DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3), + INTC_GROUP(DMAC2_2, DMAC2_2_DEI4, + DMAC2_2_DEI5, DMAC2_2_DADERR), + INTC_GROUP(DMAC3_1, DMAC3_1_DEI0, + DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3), + INTC_GROUP(DMAC3_2, DMAC3_2_DEI4, + DMAC3_2_DEI5, DMAC3_2_DADERR), + INTC_GROUP(ETM11, ETM11_ACQCMP, ETM11_FULL), + INTC_GROUP(ARM11, ARM11_IRQPMU, ARM11_COMMTX, ARM11_COMMTX), + INTC_GROUP(USBHS, USBHS_USHI0, USBHS_USHI1), + INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI, + FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), + INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1), + INTC_GROUP(SDHI0, SDHI0_SDHI0I0, SDHI0_SDHI0I1, + SDHI0_SDHI0I2, SDHI0_SDHI0I3), + INTC_GROUP(SDHI1, SDHI1_SDHI1I0, SDHI1_SDHI1I1, + SDHI1_SDHI1I2, SDHI1_SDHI1I3), + INTC_GROUP(SDHI2, SDHI2_SDHI2I0, SDHI2_SDHI2I1, + SDHI2_SDHI2I2, SDHI2_SDHI2I3), +}; + +static struct intc_mask_reg intca_mask_registers[] = { + { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */ + { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, + { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */ + { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, + { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */ + { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0, + ARM11_IRQPMU, 0, ARM11_COMMTX, ARM11_COMMRX } }, + { 0xe6940084, 0xe69400c4, 8, /* IMR1A / IMCR1A */ + { CRYPT1_ERR, CRYPT2_STD, DIRC, 0, + DMAC_1_DEI3, DMAC_1_DEI2, DMAC_1_DEI1, DMAC_1_DEI0 } }, + { 0xe6940088, 0xe69400c8, 8, /* IMR2A / IMCR2A */ + { PINT1, PINT2, 0, 0, + BBIF1, BBIF2, MFI_MFIS, MFI_MFIM } }, + { 0xe694008c, 0xe69400cc, 8, /* IMR3A / IMCR3A */ + { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0, + DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } }, + { 0xe6940090, 0xe69400d0, 8, /* IMR4A / IMCR4A */ + { DDM, 0, 0, 0, + 0, 0, ETM11_FULL, ETM11_ACQCMP } }, + { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */ + { KEYSC_KEY, DMAC_2_DADERR, DMAC_2_DEI5, DMAC_2_DEI4, + SCIFA3, SCIFA2, SCIFA1, SCIFA0 } }, + { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */ + { SCIFB, SCIFA5, SCIFA4, MSIOF1, + 0, 0, MSIOF2, 0 } }, + { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */ + { SDHI0_SDHI0I3, SDHI0_SDHI0I2, SDHI0_SDHI0I1, SDHI0_SDHI0I0, + FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, + { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */ + { SDHI1_SDHI1I3, SDHI1_SDHI1I2, SDHI1_SDHI1I1, SDHI1_SDHI1I0, + TTI20, USBDMAC_USHDMI, SPU, SIU } }, + { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */ + { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10, + CMT2, USBHS_USHI1, USBHS_USHI0, 0 } }, + { 0xe69400a8, 0xe69400e8, 8, /* IMR10A / IMCR10A */ + { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4, + 0, 0, 0, 0 } }, + { 0xe69400ac, 0xe69400ec, 8, /* IMR11A / IMCR11A */ + { IIC1_DTEI1, IIC1_WAITI1, IIC1_TACKI1, IIC1_ALI1, + LCRC, MSU_MSU2, IREM, MSU_MSU } }, + { 0xe69400b0, 0xe69400f0, 8, /* IMR12A / IMCR12A */ + { 0, 0, TPU0, TPU1, + TPU2, TPU3, TPU4, 0 } }, + { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */ + { SDHI2_SDHI2I3, SDHI2_SDHI2I2, SDHI2_SDHI2I1, SDHI2_SDHI2I0, + MISTY, CMT3, RWDT1, RWDT0 } }, +}; + +static struct intc_prio_reg intca_prio_registers[] = { + { 0xe6900010, 0, 32, 4, /* INTPRI00A */ + { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, + { 0xe6900014, 0, 32, 4, /* INTPRI10A */ + { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, + + { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, LCRC } }, + { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, ETM11, BBIF1, BBIF2 } }, + { 0xe6940008, 0, 16, 4, /* IPRCA */ { CRYPT1_ERR, CRYPT2_STD, + CMT1_CMT11, ARM11 } }, + { 0xe694000c, 0, 16, 4, /* IPRDA */ { PINT1, PINT2, + CMT1_CMT12, TPU4 } }, + { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC_1, MFI_MFIS, + MFI_MFIM, USBHS } }, + { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC_KEY, DMAC_2, + 0, CMT1_CMT10 } }, + { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1, + SCIFA2, SCIFA3 } }, + { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBDMAC_USHDMI, + FLCTL, SDHI0 } }, + { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, MSU_MSU, IIC1 } }, + { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2, SIU, TTI20 } }, + { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_CMT13, IREM, SDHI1 } }, + { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, TPU1, TPU2, TPU3 } }, + { 0xe6940030, 0, 16, 4, /* IPRMA */ { MISTY, CMT3, RWDT1, RWDT0 } }, + { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, SPU, DDM } }, + { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } }, +}; + +static struct intc_sense_reg intca_sense_registers[] __initdata = { + { 0xe6900000, 16, 2, /* ICR1A */ + { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, + { 0xe6900004, 16, 2, /* ICR2A */ + { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, +}; + +static struct intc_mask_reg intca_ack_registers[] __initdata = { + { 0xe6900020, 0, 8, /* INTREQ00A */ + { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, + { 0xe6900024, 0, 8, /* INTREQ10A */ + { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, +}; + +static DECLARE_INTC_DESC_ACK(intca_desc, "sh7367-intca", + intca_vectors, intca_groups, + intca_mask_registers, intca_prio_registers, + intca_sense_registers, intca_ack_registers); + +void __init sh7367_init_irq(void) +{ + /* INTCA */ + register_intc_controller(&intca_desc); +} --- 0002/arch/arm/mach-shmobile/setup-sh7367.c +++ work/arch/arm/mach-shmobile/setup-sh7367.c 2010-02-08 13:44:08.000000000 +0900 @@ -26,7 +26,6 @@ #include #include #include -#include #include #include #include @@ -197,45 +196,3 @@ void __init sh7367_add_early_devices(voi early_platform_add_devices(sh7367_early_devices, ARRAY_SIZE(sh7367_early_devices)); } - -enum { - UNUSED = 0, - - /* interrupt sources INTCA */ - - SCIFA0, SCIFA1, SCIFA2, SCIFA3, SCIFA4, SCIFA5, SCIFB, - CMT10, -}; - -static struct intc_vect vectors[] = { - INTC_VECT(CMT10, 0xb00), - INTC_VECT(SCIFA0, 0xc00), INTC_VECT(SCIFA1, 0xc20), - INTC_VECT(SCIFA2, 0xc40), INTC_VECT(SCIFA3, 0xc60), - INTC_VECT(SCIFA4, 0xd20), INTC_VECT(SCIFA5, 0xd40), - INTC_VECT(SCIFB, 0xd60), -}; - -static struct intc_mask_reg mask_registers[] = { - { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */ - { 0, 0, 0, 0, SCIFA3, SCIFA2, SCIFA1, SCIFA0 } }, - { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */ - { SCIFB, SCIFA5, SCIFA4, 0, 0, 0, 0, 0 } }, - { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */ - { 0, 0, 0, CMT10, 0, 0, 0, 0 } }, -}; - -static struct intc_prio_reg prio_registers[] = { - { 0xe6940014, 0, 16, 4, /* IPRFA */ { 0, 0, 0, CMT10 } }, - { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1, - SCIFA2, SCIFA3 } }, - { 0xe6940020, 0, 16, 4, /* IPRIA */ { 0, SCIFA4, 0, 0 } }, - { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, 0 } }, -}; - -static DECLARE_INTC_DESC(intc_desc, "sh7367", vectors, NULL, mask_registers, - prio_registers, NULL); - -void __init sh7367_init_irq(void) -{ - register_intc_controller(&intc_desc); -}