From patchwork Fri Mar 19 04:47:10 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Magnus Damm X-Patchwork-Id: 86876 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o2J4l1ku016568 for ; Fri, 19 Mar 2010 04:47:11 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751159Ab0CSErK (ORCPT ); Fri, 19 Mar 2010 00:47:10 -0400 Received: from mail-yw0-f198.google.com ([209.85.211.198]:51736 "EHLO mail-yw0-f198.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751154Ab0CSErJ (ORCPT ); Fri, 19 Mar 2010 00:47:09 -0400 Received: by ywh36 with SMTP id 36so474355ywh.4 for ; Thu, 18 Mar 2010 21:47:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:date:message-id :in-reply-to:references:subject; bh=MIQs64tHqznI5YOBOcJQMSNAWxUUPGfJxDgbAOL7w/8=; b=dZk7J11fklrEh3WZZ8VmaTpoa0Nv+opFlBTnKz7vQaYnUFrR2xqlte0NBfbr4POCD4 mAfnIBSucrsyjSdrVGJwp+5irss1bjDE+PyrUiMi0oDvj/eJlQHCJnVxQLwUoSE4d0ly D455V0fq6mMZj4OYytaGoR9dk+v/2P5zmZbKI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:date:message-id:in-reply-to:references:subject; b=NT2VqRt0FaQ+yGbgwZbz7jYULJvEhVdreJ7TqBjc/OhpeXNYj8dHU/BGfAPOXwyYEF J4eRN8frKHPfQ2NM6EMnuiv4YhKFdEmlbGtzLU5dfLKKy1sIJBGYSPkU3WVtOUHTiMvC Hrno8P2/YKKsRwK3K6i2DOoQuTk6tUXj1163c= Received: by 10.101.11.14 with SMTP id o14mr6007926ani.196.1268974028213; Thu, 18 Mar 2010 21:47:08 -0700 (PDT) Received: from [127.0.0.1] (49.14.32.202.bf.2iij.net [202.32.14.49]) by mx.google.com with ESMTPS id 13sm457391gxk.8.2010.03.18.21.47.06 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 18 Mar 2010 21:47:07 -0700 (PDT) From: Magnus Damm To: linux-sh@vger.kernel.org Cc: Magnus Damm , lethal@linux-sh.org, dan.j.williams@intel.com, iwamatsu@nigauri.org, g.liakhovetski@gmx.de Date: Fri, 19 Mar 2010 13:47:10 +0900 Message-Id: <20100319044710.17051.98259.sendpatchset@t400s> In-Reply-To: <20100319044630.17051.16445.sendpatchset@t400s> References: <20100319044630.17051.16445.sendpatchset@t400s> Subject: [PATCH 04/05] dmaengine: shdma: Introduce include/linux/sh_dma.h Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 19 Mar 2010 04:47:11 +0000 (UTC) --- 0004/arch/sh/include/asm/dmaengine.h +++ work/arch/sh/include/asm/dmaengine.h 2010-03-18 23:25:04.000000000 +0900 @@ -10,12 +10,7 @@ #ifndef ASM_DMAENGINE_H #define ASM_DMAENGINE_H -#include -#include - -#include - -#define SH_DMAC_MAX_CHANNELS 6 +#include enum { SHDMA_SLAVE_SCIF0_TX, @@ -36,57 +31,4 @@ enum { SHDMA_SLAVE_SIUB_RX, }; -struct sh_dmae_slave_config { - unsigned int slave_id; - dma_addr_t addr; - u32 chcr; - char mid_rid; -}; - -struct sh_dmae_channel { - unsigned int offset; - unsigned int dmars; - unsigned int dmars_bit; -}; - -struct sh_dmae_pdata { - struct sh_dmae_slave_config *slave; - int slave_num; - struct sh_dmae_channel *channel; - int channel_num; - unsigned int ts_low_shift; - unsigned int ts_low_mask; - unsigned int ts_high_shift; - unsigned int ts_high_mask; - unsigned int *ts_shift; - int ts_shift_num; - u16 dmaor_init; -}; - -struct device; - -/* Used by slave DMA clients to request DMA to/from a specific peripheral */ -struct sh_dmae_slave { - unsigned int slave_id; /* Set by the platform */ - struct device *dma_dev; /* Set by the platform */ - struct sh_dmae_slave_config *config; /* Set by the driver */ -}; - -struct sh_dmae_regs { - u32 sar; /* SAR / source address */ - u32 dar; /* DAR / destination address */ - u32 tcr; /* TCR / transfer count */ -}; - -struct sh_desc { - struct sh_dmae_regs hw; - struct list_head node; - struct dma_async_tx_descriptor async_tx; - enum dma_data_direction direction; - dma_cookie_t cookie; - size_t partial; - int chunks; - int mark; -}; - #endif --- 0004/drivers/dma/shdma.c +++ work/drivers/dma/shdma.c 2010-03-18 23:25:04.000000000 +0900 @@ -25,8 +25,7 @@ #include #include #include - -#include +#include #include "shdma.h" --- 0004/drivers/dma/shdma.h +++ work/drivers/dma/shdma.h 2010-03-18 23:25:04.000000000 +0900 @@ -17,8 +17,7 @@ #include #include -#include - +#define SH_DMAC_MAX_CHANNELS 6 #define SH_DMA_SLAVE_NUMBER 256 #define SH_DMA_TCR_MAX 0x00FFFFFF /* 16MB */ --- /dev/null +++ work/include/linux/sh_dma.h 2010-03-18 23:25:32.000000000 +0900 @@ -0,0 +1,101 @@ +/* + * Header for the new SH dmaengine driver + * + * Copyright (C) 2010 Guennadi Liakhovetski + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef SH_DMA_H +#define SH_DMA_H + +#include +#include + +/* Used by slave DMA clients to request DMA to/from a specific peripheral */ +struct sh_dmae_slave { + unsigned int slave_id; /* Set by the platform */ + struct device *dma_dev; /* Set by the platform */ + struct sh_dmae_slave_config *config; /* Set by the driver */ +}; + +struct sh_dmae_regs { + u32 sar; /* SAR / source address */ + u32 dar; /* DAR / destination address */ + u32 tcr; /* TCR / transfer count */ +}; + +struct sh_desc { + struct sh_dmae_regs hw; + struct list_head node; + struct dma_async_tx_descriptor async_tx; + enum dma_data_direction direction; + dma_cookie_t cookie; + size_t partial; + int chunks; + int mark; +}; +struct sh_dmae_slave_config { + unsigned int slave_id; + dma_addr_t addr; + u32 chcr; + char mid_rid; +}; + +struct sh_dmae_channel { + unsigned int offset; + unsigned int dmars; + unsigned int dmars_bit; +}; + +struct sh_dmae_pdata { + struct sh_dmae_slave_config *slave; + int slave_num; + struct sh_dmae_channel *channel; + int channel_num; + unsigned int ts_low_shift; + unsigned int ts_low_mask; + unsigned int ts_high_shift; + unsigned int ts_high_mask; + unsigned int *ts_shift; + int ts_shift_num; + u16 dmaor_init; +}; + +/* DMA register */ +#define SAR 0x00 +#define DAR 0x04 +#define TCR 0x08 +#define CHCR 0x0C +#define DMAOR 0x40 + +/* DMAOR definitions */ +#define DMAOR_AE 0x00000004 +#define DMAOR_NMIF 0x00000002 +#define DMAOR_DME 0x00000001 + +/* Definitions for the SuperH DMAC */ +#define REQ_L 0x00000000 +#define REQ_E 0x00080000 +#define RACK_H 0x00000000 +#define RACK_L 0x00040000 +#define ACK_R 0x00000000 +#define ACK_W 0x00020000 +#define ACK_H 0x00000000 +#define ACK_L 0x00010000 +#define DM_INC 0x00004000 +#define DM_DEC 0x00008000 +#define DM_FIX 0x0000c000 +#define SM_INC 0x00001000 +#define SM_DEC 0x00002000 +#define SM_FIX 0x00003000 +#define RS_IN 0x00000200 +#define RS_OUT 0x00000300 +#define TS_BLK 0x00000040 +#define TM_BUR 0x00000020 +#define CHCR_DE 0x00000001 +#define CHCR_TE 0x00000002 +#define CHCR_IE 0x00000004 + +#endif