From patchwork Wed May 12 08:35:06 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Magnus Damm X-Patchwork-Id: 98944 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4C8XjWT027455 for ; Wed, 12 May 2010 08:33:57 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754690Ab0ELId4 (ORCPT ); Wed, 12 May 2010 04:33:56 -0400 Received: from mail-pv0-f174.google.com ([74.125.83.174]:61532 "EHLO mail-pv0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753524Ab0ELIdz (ORCPT ); Wed, 12 May 2010 04:33:55 -0400 Received: by pvh11 with SMTP id 11so334683pvh.19 for ; Wed, 12 May 2010 01:33:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:date:message-id :in-reply-to:references:subject; bh=Ih1woi4m61vdUNJ1hpYe1cGF8uN5POGd2Chf0V1V8Nc=; b=t4y3tvPuJUfIQdJLBtn6uGh+eZ32m9713QoxplRezMy9eXRXWK6yejXe1HpXBj53eT d1Lrs4szdREAho3hypTtB5E1wQJEmDjg28nygbRhMzCsuM+Ak5Uh5CsURFOu3JGjTnjt zfIlFOkuCfFO5ubyKWoqTCqIuvdS8vHj71y84= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:date:message-id:in-reply-to:references:subject; b=R0NprLdPZftdloW3i1a1MEc0DEbZk9g7CZmKJvN44H3q8Y5hMNxakHkf2n3UfsDqLq s7LyhWk/ByrsLGNXnME89HFl7WxbVkXYnw+tOufYwHvFup98FffR7SP2KMh5M/9eVKn4 xkYd0VgFp4iEDaHsNLP9XquXf7C3uYGB/PFaI= Received: by 10.114.19.34 with SMTP id 34mr5524196was.188.1273653234797; Wed, 12 May 2010 01:33:54 -0700 (PDT) Received: from [127.0.0.1] (49.14.32.202.bf.2iij.net [202.32.14.49]) by mx.google.com with ESMTPS id v13sm42658892wav.14.2010.05.12.01.33.53 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 12 May 2010 01:33:54 -0700 (PDT) From: Magnus Damm To: linux-sh@vger.kernel.org Cc: Magnus Damm , lethal@linux-sh.org Date: Wed, 12 May 2010 17:35:06 +0900 Message-Id: <20100512083506.9395.36222.sendpatchset@t400s> In-Reply-To: <20100512083443.9395.90768.sendpatchset@t400s> References: <20100512083443.9395.90768.sendpatchset@t400s> Subject: [PATCH 03/05] ARM: mach-shmobile: UIO platform data for sh7372 Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 12 May 2010 08:33:58 +0000 (UTC) --- 0001/arch/arm/mach-shmobile/setup-sh7372.c +++ work/arch/arm/mach-shmobile/setup-sh7372.c 2010-05-12 16:53:57.000000000 +0900 @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -29,6 +30,7 @@ #include #include #include +#include #include #include @@ -214,6 +216,238 @@ static struct platform_device iic1_devic .resource = iic1_resources, }; +/* VPU */ +static struct uio_info vpu_platform_data = { + .name = "VPU5HG", + .version = "0", + .irq = intcs_evt2irq(0x980), +}; + +static struct resource vpu_resources[] = { + [0] = { + .name = "VPU", + .start = 0xfe900000, + .end = 0xfe900157, + .flags = IORESOURCE_MEM, + }, + [1] = { + /* place holder for contiguous memory */ + }, +}; + +static struct platform_device vpu_device = { + .name = "uio_pdrv_genirq", + .id = 0, + .dev = { + .platform_data = &vpu_platform_data, + }, + .resource = vpu_resources, + .num_resources = ARRAY_SIZE(vpu_resources), +}; + +/* VEU0 */ +static struct uio_info veu0_platform_data = { + .name = "VEU0", + .version = "0", + .irq = intcs_evt2irq(0x700), +}; + +static struct resource veu0_resources[] = { + [0] = { + .name = "VEU0", + .start = 0xfe920000, + .end = 0xfe9200cb, + .flags = IORESOURCE_MEM, + }, + [1] = { + /* place holder for contiguous memory */ + }, +}; + +static struct platform_device veu0_device = { + .name = "uio_pdrv_genirq", + .id = 1, + .dev = { + .platform_data = &veu0_platform_data, + }, + .resource = veu0_resources, + .num_resources = ARRAY_SIZE(veu0_resources), +}; + +/* VEU1 */ +static struct uio_info veu1_platform_data = { + .name = "VEU1", + .version = "0", + .irq = intcs_evt2irq(0x720), +}; + +static struct resource veu1_resources[] = { + [0] = { + .name = "VEU1", + .start = 0xfe924000, + .end = 0xfe9240cb, + .flags = IORESOURCE_MEM, + }, + [1] = { + /* place holder for contiguous memory */ + }, +}; + +static struct platform_device veu1_device = { + .name = "uio_pdrv_genirq", + .id = 2, + .dev = { + .platform_data = &veu1_platform_data, + }, + .resource = veu1_resources, + .num_resources = ARRAY_SIZE(veu1_resources), +}; + +/* VEU2 */ +static struct uio_info veu2_platform_data = { + .name = "VEU2", + .version = "0", + .irq = intcs_evt2irq(0x740), +}; + +static struct resource veu2_resources[] = { + [0] = { + .name = "VEU2", + .start = 0xfe928000, + .end = 0xfe928307, + .flags = IORESOURCE_MEM, + }, + [1] = { + /* place holder for contiguous memory */ + }, +}; + +static struct platform_device veu2_device = { + .name = "uio_pdrv_genirq", + .id = 3, + .dev = { + .platform_data = &veu2_platform_data, + }, + .resource = veu2_resources, + .num_resources = ARRAY_SIZE(veu2_resources), +}; + +/* VEU3 */ +static struct uio_info veu3_platform_data = { + .name = "VEU3", + .version = "0", + .irq = intcs_evt2irq(0x760), +}; + +static struct resource veu3_resources[] = { + [0] = { + .name = "VEU3", + .start = 0xfe92c000, + .end = 0xfe92c307, + .flags = IORESOURCE_MEM, + }, + [1] = { + /* place holder for contiguous memory */ + }, +}; + +static struct platform_device veu3_device = { + .name = "uio_pdrv_genirq", + .id = 4, + .dev = { + .platform_data = &veu3_platform_data, + }, + .resource = veu3_resources, + .num_resources = ARRAY_SIZE(veu3_resources), +}; + +/* JPU */ +static struct uio_info jpu_platform_data = { + .name = "JPU", + .version = "0", + .irq = intcs_evt2irq(0x560), +}; + +static struct resource jpu_resources[] = { + [0] = { + .name = "JPU", + .start = 0xfe980000, + .end = 0xfe9902d3, + .flags = IORESOURCE_MEM, + }, + [1] = { + /* place holder for contiguous memory */ + }, +}; + +static struct platform_device jpu_device = { + .name = "uio_pdrv_genirq", + .id = 5, + .dev = { + .platform_data = &jpu_platform_data, + }, + .resource = jpu_resources, + .num_resources = ARRAY_SIZE(jpu_resources), +}; + +/* SPU2DSP0 */ +static struct uio_info spu0_platform_data = { + .name = "SPU2DSP0", + .version = "0", + .irq = evt2irq(0x1800), +}; + +static struct resource spu0_resources[] = { + [0] = { + .name = "SPU2DSP0", + .start = 0xFE200000, + .end = 0xFE2FFFFF, + .flags = IORESOURCE_MEM, + }, + [1] = { + /* place holder for contiguous memory */ + }, +}; + +static struct platform_device spu0_device = { + .name = "uio_pdrv_genirq", + .id = 6, + .dev = { + .platform_data = &spu0_platform_data, + }, + .resource = spu0_resources, + .num_resources = ARRAY_SIZE(spu0_resources), +}; + +/* SPU2DSP1 */ +static struct uio_info spu1_platform_data = { + .name = "SPU2DSP1", + .version = "0", + .irq = evt2irq(0x1820), +}; + +static struct resource spu1_resources[] = { + [0] = { + .name = "SPU2DSP1", + .start = 0xFE300000, + .end = 0xFE3FFFFF, + .flags = IORESOURCE_MEM, + }, + [1] = { + /* place holder for contiguous memory */ + }, +}; + +static struct platform_device spu1_device = { + .name = "uio_pdrv_genirq", + .id = 7, + .dev = { + .platform_data = &spu1_platform_data, + }, + .resource = spu1_resources, + .num_resources = ARRAY_SIZE(spu1_resources), +}; + static struct platform_device *sh7372_early_devices[] __initdata = { &scif0_device, &scif1_device, @@ -223,14 +457,37 @@ static struct platform_device *sh7372_ea &scif5_device, &scif6_device, &cmt10_device, +}; + +static struct platform_device *sh7372_devices[] __initdata = { &iic0_device, &iic1_device, + &vpu_device, + &veu0_device, + &veu1_device, + &veu2_device, + &veu3_device, + &jpu_device, + &spu0_device, + &spu1_device, }; void __init sh7372_add_standard_devices(void) { platform_add_devices(sh7372_early_devices, ARRAY_SIZE(sh7372_early_devices)); + + platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20); + platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20); + platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20); + platform_resource_setup_memory(&veu2_device, "veu2", 2 << 20); + platform_resource_setup_memory(&veu3_device, "veu3", 2 << 20); + platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20); + platform_resource_setup_memory(&spu0_device, "spu0", 2 << 20); + platform_resource_setup_memory(&spu1_device, "spu1", 2 << 20); + + platform_add_devices(sh7372_devices, + ARRAY_SIZE(sh7372_devices)); } #define SMSTPCR3 0xe615013c