From patchwork Wed Dec 12 10:33:38 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Pieralisi X-Patchwork-Id: 1865461 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 9FE9E4006E for ; Wed, 12 Dec 2012 10:35:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751884Ab2LLKfG (ORCPT ); Wed, 12 Dec 2012 05:35:06 -0500 Received: from service87.mimecast.com ([91.220.42.44]:34622 "EHLO service87.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751152Ab2LLKfF convert rfc822-to-8bit (ORCPT ); Wed, 12 Dec 2012 05:35:05 -0500 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Wed, 12 Dec 2012 10:33:44 +0000 Received: from e102568-lin.cambridge.arm.com ([10.1.255.212]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 12 Dec 2012 10:33:39 +0000 Date: Wed, 12 Dec 2012 10:33:38 +0000 From: Lorenzo Pieralisi To: Stephen Boyd Cc: Will Deacon , Guennadi Liakhovetski , Nicolas Pitre , Dave Martin , Russell King , "linux-sh@vger.kernel.org" , Catalin Marinas , Daniel Lezcano , Amit Kucheria , Simon Horman , Santosh Shilimkar , Colin Cross , "linux-omap@vger.kernel.org" , Wenzeng Chen , "linux-arm-kernel@lists.infradead.org" Subject: Re: [RFC PATCH v2 3/5] ARM: kernel: update cpu_suspend code to use cache LoUIS operations Message-ID: <20121212103338.GB23022@e102568-lin.cambridge.arm.com> References: <1347986135-17979-1-git-send-email-lorenzo.pieralisi@arm.com> <1347986135-17979-4-git-send-email-lorenzo.pieralisi@arm.com> <20120919134658.GA2111@linaro.org> <20120920102514.GD4588@e102568-lin.cambridge.arm.com> <20120920110439.GB2117@linaro.org> <20121211163313.GG16759@mudshark.cambridge.arm.com> <20121211163843.GH16759@mudshark.cambridge.arm.com> <50C7C16B.7050106@codeaurora.org> MIME-Version: 1.0 In-Reply-To: <50C7C16B.7050106@codeaurora.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-OriginalArrivalTime: 12 Dec 2012 10:33:39.0631 (UTC) FILETIME=[26604BF0:01CDD854] X-MC-Unique: 112121210340505301 Content-Disposition: inline Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org On Tue, Dec 11, 2012 at 11:27:39PM +0000, Stephen Boyd wrote: > On 12/11/12 08:38, Will Deacon wrote: > > diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S > > index cd95664..f58248f 100644 > > --- a/arch/arm/mm/cache-v7.S > > +++ b/arch/arm/mm/cache-v7.S > > @@ -44,7 +44,8 @@ ENDPROC(v7_flush_icache_all) > > ENTRY(v7_flush_dcache_louis) > > dmb @ ensure ordering with previous memory accesses > > mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr > > - ands r3, r0, #0xe00000 @ extract LoUIS from clidr > > + ALT_SMP(ands r3, r0, #(7 << 21)) @ extract LoUIS from clidr > > + ALT_UP(ands r3, r0, #(7 << 27)) @ extract LoUU from clidr > > mov r3, r3, lsr #20 @ r3 = LoUIS * 2 > > You need to fix this mov as well, right? And after doing that I think the suspend finisher will still have to call flush_cache_all() since LoUU == 1 on A8, L2 is not cleaned and that's probably what we want if it can be retained. What about this (compile tested) ? Lorenzo --->8 --- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index cd95664..036f80f 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -44,8 +44,9 @@ ENDPROC(v7_flush_icache_all) ENTRY(v7_flush_dcache_louis) dmb @ ensure ordering with previous memory accesses mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr - ands r3, r0, #0xe00000 @ extract LoUIS from clidr - mov r3, r3, lsr #20 @ r3 = LoUIS * 2 + ALT_SMP(lsr r3, r0, #20) @ r3 = clidr[31:20] + ALT_UP(lsr r3, r0, #26) @ r3 = clidr[31:26] + ands r3, r3, #0xe @ r3 = LoUIS/LoUU * 2 moveq pc, lr @ return if level == 0 mov r10, #0 @ r10 (starting level) = 0 b flush_levels @ start flushing cache levels