From patchwork Thu Mar 28 21:48:26 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 2359401 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id C8F003FD40 for ; Thu, 28 Mar 2013 20:47:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751576Ab3C1Uq7 (ORCPT ); Thu, 28 Mar 2013 16:46:59 -0400 Received: from mail-la0-f53.google.com ([209.85.215.53]:55841 "EHLO mail-la0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751279Ab3C1Uq6 (ORCPT ); Thu, 28 Mar 2013 16:46:58 -0400 Received: by mail-la0-f53.google.com with SMTP id fr10so18158512lab.26 for ; Thu, 28 Mar 2013 13:46:56 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:to:subject:cc:from:organization:date:mime-version :content-type:content-transfer-encoding:message-id :x-gm-message-state; bh=TI6lB00U2A1RCMi+3S7VYGmWeJiHLzNDr9+Rz8O8gjQ=; b=Ntnb0stHRXeB1XWrfQ3puf7C2Ut7O3tYtd+zlAr+XYWjZtLgKJ/FMWR0xmy1wzvLc7 +ZfhVz1a4ijaFBWd6Pg7pR21C3G4hIzdA5WZE54/zoPELJsZJydDOpIbwgkl6KVWp5kY aF2SJPlkAxuTIR1VdFb1a6VTa0Lit+mHmDUYp4Mzje6x+ami5yquftUEr4d1iZ5U4qoi 8EZvgCO8ZF7rYyuv7qli+uXmHSMiFB+l60wNfdq/PDqSQ+D7OxmZVCu49kGGzFfpTuhK LS9pPYOPJDsBO7UFFhjNMJss1LgbFxSnwxQHjpD5VTt31SEoa0mmylldbTmC4+WmGVsH qteQ== X-Received: by 10.112.9.231 with SMTP id d7mr308339lbb.8.1364503616629; Thu, 28 Mar 2013 13:46:56 -0700 (PDT) Received: from wasted.dev.rtsoft.ru (ppp91-79-65-245.pppoe.mtu-net.ru. [91.79.65.245]) by mx.google.com with ESMTPS id mq7sm57911lab.1.2013.03.28.13.46.54 (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 28 Mar 2013 13:46:55 -0700 (PDT) To: netdev@vger.kernel.org Subject: [PATCH 1/2] sh_eth: move data from header file to driver Cc: nobuhiro.iwamatsu.yj@renesas.com, linux-sh@vger.kernel.org From: Sergei Shtylyov Organization: Cogent Embedded Date: Fri, 29 Mar 2013 00:48:26 +0300 MIME-Version: 1.0 Message-Id: <201303290048.27020.sergei.shtylyov@cogentembedded.com> X-Gm-Message-State: ALoCoQkAPZmdU8getjKeVAOYpDXk+hVVsfMZ6HLt0tYyHWaQbqxY+wm7w7tSE1vkj+7CNerpuLV7 Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org The driver's header file contains initialized register offset tables which (as any data definitions), of course, have no business being there. Move them to the driver's body, somewhat beautifying the initializers, while at it... Signed-off-by: Sergei Shtylyov --- The patch is against the David Miller's 'net-next.git' repo. drivers/net/ethernet/renesas/sh_eth.c | 218 +++++++++++++++++++++++++++++++++ drivers/net/ethernet/renesas/sh_eth.h | 219 ---------------------------------- 2 files changed, 218 insertions(+), 219 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Index: net-next/drivers/net/ethernet/renesas/sh_eth.c =================================================================== --- net-next.orig/drivers/net/ethernet/renesas/sh_eth.c +++ net-next/drivers/net/ethernet/renesas/sh_eth.c @@ -49,6 +49,224 @@ NETIF_MSG_RX_ERR| \ NETIF_MSG_TX_ERR) +static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = { + [EDSR] = 0x0000, + [EDMR] = 0x0400, + [EDTRR] = 0x0408, + [EDRRR] = 0x0410, + [EESR] = 0x0428, + [EESIPR] = 0x0430, + [TDLAR] = 0x0010, + [TDFAR] = 0x0014, + [TDFXR] = 0x0018, + [TDFFR] = 0x001c, + [RDLAR] = 0x0030, + [RDFAR] = 0x0034, + [RDFXR] = 0x0038, + [RDFFR] = 0x003c, + [TRSCER] = 0x0438, + [RMFCR] = 0x0440, + [TFTR] = 0x0448, + [FDR] = 0x0450, + [RMCR] = 0x0458, + [RPADIR] = 0x0460, + [FCFTR] = 0x0468, + [CSMR] = 0x04E4, + + [ECMR] = 0x0500, + [ECSR] = 0x0510, + [ECSIPR] = 0x0518, + [PIR] = 0x0520, + [PSR] = 0x0528, + [PIPR] = 0x052c, + [RFLR] = 0x0508, + [APR] = 0x0554, + [MPR] = 0x0558, + [PFTCR] = 0x055c, + [PFRCR] = 0x0560, + [TPAUSER] = 0x0564, + [GECMR] = 0x05b0, + [BCULR] = 0x05b4, + [MAHR] = 0x05c0, + [MALR] = 0x05c8, + [TROCR] = 0x0700, + [CDCR] = 0x0708, + [LCCR] = 0x0710, + [CEFCR] = 0x0740, + [FRECR] = 0x0748, + [TSFRCR] = 0x0750, + [TLFRCR] = 0x0758, + [RFCR] = 0x0760, + [CERCR] = 0x0768, + [CEECR] = 0x0770, + [MAFCR] = 0x0778, + [RMII_MII] = 0x0790, + + [ARSTR] = 0x0000, + [TSU_CTRST] = 0x0004, + [TSU_FWEN0] = 0x0010, + [TSU_FWEN1] = 0x0014, + [TSU_FCM] = 0x0018, + [TSU_BSYSL0] = 0x0020, + [TSU_BSYSL1] = 0x0024, + [TSU_PRISL0] = 0x0028, + [TSU_PRISL1] = 0x002c, + [TSU_FWSL0] = 0x0030, + [TSU_FWSL1] = 0x0034, + [TSU_FWSLC] = 0x0038, + [TSU_QTAG0] = 0x0040, + [TSU_QTAG1] = 0x0044, + [TSU_FWSR] = 0x0050, + [TSU_FWINMK] = 0x0054, + [TSU_ADQT0] = 0x0048, + [TSU_ADQT1] = 0x004c, + [TSU_VTAG0] = 0x0058, + [TSU_VTAG1] = 0x005c, + [TSU_ADSBSY] = 0x0060, + [TSU_TEN] = 0x0064, + [TSU_POST1] = 0x0070, + [TSU_POST2] = 0x0074, + [TSU_POST3] = 0x0078, + [TSU_POST4] = 0x007c, + [TSU_ADRH0] = 0x0100, + [TSU_ADRL0] = 0x0104, + [TSU_ADRH31] = 0x01f8, + [TSU_ADRL31] = 0x01fc, + + [TXNLCR0] = 0x0080, + [TXALCR0] = 0x0084, + [RXNLCR0] = 0x0088, + [RXALCR0] = 0x008c, + [FWNLCR0] = 0x0090, + [FWALCR0] = 0x0094, + [TXNLCR1] = 0x00a0, + [TXALCR1] = 0x00a0, + [RXNLCR1] = 0x00a8, + [RXALCR1] = 0x00ac, + [FWNLCR1] = 0x00b0, + [FWALCR1] = 0x00b4, +}; + +static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { + [ECMR] = 0x0100, + [RFLR] = 0x0108, + [ECSR] = 0x0110, + [ECSIPR] = 0x0118, + [PIR] = 0x0120, + [PSR] = 0x0128, + [RDMLR] = 0x0140, + [IPGR] = 0x0150, + [APR] = 0x0154, + [MPR] = 0x0158, + [TPAUSER] = 0x0164, + [RFCF] = 0x0160, + [TPAUSECR] = 0x0168, + [BCFRR] = 0x016c, + [MAHR] = 0x01c0, + [MALR] = 0x01c8, + [TROCR] = 0x01d0, + [CDCR] = 0x01d4, + [LCCR] = 0x01d8, + [CNDCR] = 0x01dc, + [CEFCR] = 0x01e4, + [FRECR] = 0x01e8, + [TSFRCR] = 0x01ec, + [TLFRCR] = 0x01f0, + [RFCR] = 0x01f4, + [MAFCR] = 0x01f8, + [RTRATE] = 0x01fc, + + [EDMR] = 0x0000, + [EDTRR] = 0x0008, + [EDRRR] = 0x0010, + [TDLAR] = 0x0018, + [RDLAR] = 0x0020, + [EESR] = 0x0028, + [EESIPR] = 0x0030, + [TRSCER] = 0x0038, + [RMFCR] = 0x0040, + [TFTR] = 0x0048, + [FDR] = 0x0050, + [RMCR] = 0x0058, + [TFUCR] = 0x0064, + [RFOCR] = 0x0068, + [FCFTR] = 0x0070, + [RPADIR] = 0x0078, + [TRIMD] = 0x007c, + [RBWAR] = 0x00c8, + [RDFAR] = 0x00cc, + [TBRAR] = 0x00d4, + [TDFAR] = 0x00d8, +}; + +static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = { + [ECMR] = 0x0160, + [ECSR] = 0x0164, + [ECSIPR] = 0x0168, + [PIR] = 0x016c, + [MAHR] = 0x0170, + [MALR] = 0x0174, + [RFLR] = 0x0178, + [PSR] = 0x017c, + [TROCR] = 0x0180, + [CDCR] = 0x0184, + [LCCR] = 0x0188, + [CNDCR] = 0x018c, + [CEFCR] = 0x0194, + [FRECR] = 0x0198, + [TSFRCR] = 0x019c, + [TLFRCR] = 0x01a0, + [RFCR] = 0x01a4, + [MAFCR] = 0x01a8, + [IPGR] = 0x01b4, + [APR] = 0x01b8, + [MPR] = 0x01bc, + [TPAUSER] = 0x01c4, + [BCFR] = 0x01cc, + + [ARSTR] = 0x0000, + [TSU_CTRST] = 0x0004, + [TSU_FWEN0] = 0x0010, + [TSU_FWEN1] = 0x0014, + [TSU_FCM] = 0x0018, + [TSU_BSYSL0] = 0x0020, + [TSU_BSYSL1] = 0x0024, + [TSU_PRISL0] = 0x0028, + [TSU_PRISL1] = 0x002c, + [TSU_FWSL0] = 0x0030, + [TSU_FWSL1] = 0x0034, + [TSU_FWSLC] = 0x0038, + [TSU_QTAGM0] = 0x0040, + [TSU_QTAGM1] = 0x0044, + [TSU_ADQT0] = 0x0048, + [TSU_ADQT1] = 0x004c, + [TSU_FWSR] = 0x0050, + [TSU_FWINMK] = 0x0054, + [TSU_ADSBSY] = 0x0060, + [TSU_TEN] = 0x0064, + [TSU_POST1] = 0x0070, + [TSU_POST2] = 0x0074, + [TSU_POST3] = 0x0078, + [TSU_POST4] = 0x007c, + + [TXNLCR0] = 0x0080, + [TXALCR0] = 0x0084, + [RXNLCR0] = 0x0088, + [RXALCR0] = 0x008c, + [FWNLCR0] = 0x0090, + [FWALCR0] = 0x0094, + [TXNLCR1] = 0x00a0, + [TXALCR1] = 0x00a0, + [RXNLCR1] = 0x00a8, + [RXALCR1] = 0x00ac, + [FWNLCR1] = 0x00b0, + [FWALCR1] = 0x00b4, + + [TSU_ADRH0] = 0x0100, + [TSU_ADRL0] = 0x0104, + [TSU_ADRL31] = 0x01fc, +}; + #if defined(CONFIG_CPU_SUBTYPE_SH7734) || \ defined(CONFIG_CPU_SUBTYPE_SH7763) || \ defined(CONFIG_ARCH_R8A7740) Index: net-next/drivers/net/ethernet/renesas/sh_eth.h =================================================================== --- net-next.orig/drivers/net/ethernet/renesas/sh_eth.h +++ net-next/drivers/net/ethernet/renesas/sh_eth.h @@ -156,225 +156,6 @@ enum { SH_ETH_MAX_REGISTER_OFFSET, }; -static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = { - [EDSR] = 0x0000, - [EDMR] = 0x0400, - [EDTRR] = 0x0408, - [EDRRR] = 0x0410, - [EESR] = 0x0428, - [EESIPR] = 0x0430, - [TDLAR] = 0x0010, - [TDFAR] = 0x0014, - [TDFXR] = 0x0018, - [TDFFR] = 0x001c, - [RDLAR] = 0x0030, - [RDFAR] = 0x0034, - [RDFXR] = 0x0038, - [RDFFR] = 0x003c, - [TRSCER] = 0x0438, - [RMFCR] = 0x0440, - [TFTR] = 0x0448, - [FDR] = 0x0450, - [RMCR] = 0x0458, - [RPADIR] = 0x0460, - [FCFTR] = 0x0468, - [CSMR] = 0x04E4, - - [ECMR] = 0x0500, - [ECSR] = 0x0510, - [ECSIPR] = 0x0518, - [PIR] = 0x0520, - [PSR] = 0x0528, - [PIPR] = 0x052c, - [RFLR] = 0x0508, - [APR] = 0x0554, - [MPR] = 0x0558, - [PFTCR] = 0x055c, - [PFRCR] = 0x0560, - [TPAUSER] = 0x0564, - [GECMR] = 0x05b0, - [BCULR] = 0x05b4, - [MAHR] = 0x05c0, - [MALR] = 0x05c8, - [TROCR] = 0x0700, - [CDCR] = 0x0708, - [LCCR] = 0x0710, - [CEFCR] = 0x0740, - [FRECR] = 0x0748, - [TSFRCR] = 0x0750, - [TLFRCR] = 0x0758, - [RFCR] = 0x0760, - [CERCR] = 0x0768, - [CEECR] = 0x0770, - [MAFCR] = 0x0778, - [RMII_MII] = 0x0790, - - [ARSTR] = 0x0000, - [TSU_CTRST] = 0x0004, - [TSU_FWEN0] = 0x0010, - [TSU_FWEN1] = 0x0014, - [TSU_FCM] = 0x0018, - [TSU_BSYSL0] = 0x0020, - [TSU_BSYSL1] = 0x0024, - [TSU_PRISL0] = 0x0028, - [TSU_PRISL1] = 0x002c, - [TSU_FWSL0] = 0x0030, - [TSU_FWSL1] = 0x0034, - [TSU_FWSLC] = 0x0038, - [TSU_QTAG0] = 0x0040, - [TSU_QTAG1] = 0x0044, - [TSU_FWSR] = 0x0050, - [TSU_FWINMK] = 0x0054, - [TSU_ADQT0] = 0x0048, - [TSU_ADQT1] = 0x004c, - [TSU_VTAG0] = 0x0058, - [TSU_VTAG1] = 0x005c, - [TSU_ADSBSY] = 0x0060, - [TSU_TEN] = 0x0064, - [TSU_POST1] = 0x0070, - [TSU_POST2] = 0x0074, - [TSU_POST3] = 0x0078, - [TSU_POST4] = 0x007c, - [TSU_ADRH0] = 0x0100, - [TSU_ADRL0] = 0x0104, - [TSU_ADRH31] = 0x01f8, - [TSU_ADRL31] = 0x01fc, - - [TXNLCR0] = 0x0080, - [TXALCR0] = 0x0084, - [RXNLCR0] = 0x0088, - [RXALCR0] = 0x008c, - [FWNLCR0] = 0x0090, - [FWALCR0] = 0x0094, - [TXNLCR1] = 0x00a0, - [TXALCR1] = 0x00a0, - [RXNLCR1] = 0x00a8, - [RXALCR1] = 0x00ac, - [FWNLCR1] = 0x00b0, - [FWALCR1] = 0x00b4, -}; - -static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { - [ECMR] = 0x0100, - [RFLR] = 0x0108, - [ECSR] = 0x0110, - [ECSIPR] = 0x0118, - [PIR] = 0x0120, - [PSR] = 0x0128, - [RDMLR] = 0x0140, - [IPGR] = 0x0150, - [APR] = 0x0154, - [MPR] = 0x0158, - [TPAUSER] = 0x0164, - [RFCF] = 0x0160, - [TPAUSECR] = 0x0168, - [BCFRR] = 0x016c, - [MAHR] = 0x01c0, - [MALR] = 0x01c8, - [TROCR] = 0x01d0, - [CDCR] = 0x01d4, - [LCCR] = 0x01d8, - [CNDCR] = 0x01dc, - [CEFCR] = 0x01e4, - [FRECR] = 0x01e8, - [TSFRCR] = 0x01ec, - [TLFRCR] = 0x01f0, - [RFCR] = 0x01f4, - [MAFCR] = 0x01f8, - [RTRATE] = 0x01fc, - - [EDMR] = 0x0000, - [EDTRR] = 0x0008, - [EDRRR] = 0x0010, - [TDLAR] = 0x0018, - [RDLAR] = 0x0020, - [EESR] = 0x0028, - [EESIPR] = 0x0030, - [TRSCER] = 0x0038, - [RMFCR] = 0x0040, - [TFTR] = 0x0048, - [FDR] = 0x0050, - [RMCR] = 0x0058, - [TFUCR] = 0x0064, - [RFOCR] = 0x0068, - [FCFTR] = 0x0070, - [RPADIR] = 0x0078, - [TRIMD] = 0x007c, - [RBWAR] = 0x00c8, - [RDFAR] = 0x00cc, - [TBRAR] = 0x00d4, - [TDFAR] = 0x00d8, -}; - -static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = { - [ECMR] = 0x0160, - [ECSR] = 0x0164, - [ECSIPR] = 0x0168, - [PIR] = 0x016c, - [MAHR] = 0x0170, - [MALR] = 0x0174, - [RFLR] = 0x0178, - [PSR] = 0x017c, - [TROCR] = 0x0180, - [CDCR] = 0x0184, - [LCCR] = 0x0188, - [CNDCR] = 0x018c, - [CEFCR] = 0x0194, - [FRECR] = 0x0198, - [TSFRCR] = 0x019c, - [TLFRCR] = 0x01a0, - [RFCR] = 0x01a4, - [MAFCR] = 0x01a8, - [IPGR] = 0x01b4, - [APR] = 0x01b8, - [MPR] = 0x01bc, - [TPAUSER] = 0x01c4, - [BCFR] = 0x01cc, - - [ARSTR] = 0x0000, - [TSU_CTRST] = 0x0004, - [TSU_FWEN0] = 0x0010, - [TSU_FWEN1] = 0x0014, - [TSU_FCM] = 0x0018, - [TSU_BSYSL0] = 0x0020, - [TSU_BSYSL1] = 0x0024, - [TSU_PRISL0] = 0x0028, - [TSU_PRISL1] = 0x002c, - [TSU_FWSL0] = 0x0030, - [TSU_FWSL1] = 0x0034, - [TSU_FWSLC] = 0x0038, - [TSU_QTAGM0] = 0x0040, - [TSU_QTAGM1] = 0x0044, - [TSU_ADQT0] = 0x0048, - [TSU_ADQT1] = 0x004c, - [TSU_FWSR] = 0x0050, - [TSU_FWINMK] = 0x0054, - [TSU_ADSBSY] = 0x0060, - [TSU_TEN] = 0x0064, - [TSU_POST1] = 0x0070, - [TSU_POST2] = 0x0074, - [TSU_POST3] = 0x0078, - [TSU_POST4] = 0x007c, - - [TXNLCR0] = 0x0080, - [TXALCR0] = 0x0084, - [RXNLCR0] = 0x0088, - [RXALCR0] = 0x008c, - [FWNLCR0] = 0x0090, - [FWALCR0] = 0x0094, - [TXNLCR1] = 0x00a0, - [TXALCR1] = 0x00a0, - [RXNLCR1] = 0x00a8, - [RXALCR1] = 0x00ac, - [FWNLCR1] = 0x00b0, - [FWALCR1] = 0x00b4, - - [TSU_ADRH0] = 0x0100, - [TSU_ADRL0] = 0x0104, - [TSU_ADRL31] = 0x01fc, - -}; - /* Driver's parameters */ #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE) #define SH4_SKB_RX_ALIGN 32