From patchwork Tue Apr 9 22:37:49 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 2418191 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 36ADC3FC71 for ; Tue, 9 Apr 2013 22:38:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933158Ab3DIWiw (ORCPT ); Tue, 9 Apr 2013 18:38:52 -0400 Received: from mail-lb0-f182.google.com ([209.85.217.182]:59121 "EHLO mail-lb0-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754795Ab3DIWiw (ORCPT ); Tue, 9 Apr 2013 18:38:52 -0400 Received: by mail-lb0-f182.google.com with SMTP id z13so7206154lbh.41 for ; Tue, 09 Apr 2013 15:38:50 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:to:subject:cc:from:organization:date:mime-version :content-type:content-transfer-encoding:message-id :x-gm-message-state; bh=AjTc5P6ukvUhAokiuO2gxgxJHp93EYVI02h4UeOhZe0=; b=mUgKMiQHgxMlzcj5a4PB4X8ugUYiam4nRtu9WBpv6tsOuBRTI/1Gdn0OeIRTyabgJx XZm0UcB46QIc+qF0/qtCtvZzXIjtOMxvuwh6Gqi5tx2DlF8PvoBQDkEK4T9xvcXU00DW iojHA+bMAcEA3pnZgpP7C3df0nPeWGseJjDevpPZ5rUxWtmVoStFvagzMFvXytdjWT7r TM01nl9TooqjROT8jI+6wZuXNp9hezeIn6RkM4PKsjySOGx5DY7so0pedBPI4QB7o/li kWEFxUsOv0B80ID8tcT/Yg4uPDd9yCIYfIiIpatnwG/Te6Co3bBTKeJwC+zamf2o1nvG 4tLA== X-Received: by 10.112.168.135 with SMTP id zw7mr8458460lbb.115.1365547130659; Tue, 09 Apr 2013 15:38:50 -0700 (PDT) Received: from wasted.dev.rtsoft.ru (ppp91-79-87-206.pppoe.mtu-net.ru. [91.79.87.206]) by mx.google.com with ESMTPS id b2sm6700021lbv.4.2013.04.09.15.38.49 (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 09 Apr 2013 15:38:49 -0700 (PDT) To: linux-usb@vger.kernel.org, gregkh@linuxfoundation.org Subject: [PATCH v3 7/9] rcar-phy: add platform data Cc: linux-sh@vger.kernel.org, balbi@ti.com From: Sergei Shtylyov Organization: Cogent Embedded Date: Wed, 10 Apr 2013 02:37:49 +0400 MIME-Version: 1.0 Message-Id: <201304100237.50334.sergei.shtylyov@cogentembedded.com> X-Gm-Message-State: ALoCoQkUuacK1KgmwOuRh9c4xn9zr2N041RoeUdlJqQiIm8xZv7v9pLgvhCOd/qZNtlWfVuT8ET5 Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org Currently the driver hard-codes USBPCTRL0 register to 0. It is wrong since this register contains board-specific USB ports configuration and so its value should be somehow passed via the platform data. Add file with the USBPCTRL0 bit #define's and 'struct rcar_phy_platform_data' containing the value to be set by the driver to that register. Signed-off-by: Sergei Shtylyov Acked-by: Kuninori Morimoto Acked-by: Simon Horman --- Changes since version 2: - added #include ; - added ACKs from Simon Horman and Kuninori Morimoto. include/linux/usb/rcar-phy.h | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Index: renesas/include/linux/usb/rcar-phy.h =================================================================== --- /dev/null +++ renesas/include/linux/usb/rcar-phy.h @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Cogent Embedded, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __RCAR_PHY_H +#define __RCAR_PHY_H + +#include +#include + +/* USBPCTRL0 register bits */ +#define USBPCTRL0_OVC2 BIT(10) /* Switches the OVC input pin for port 2: */ + /* 1: USB_OVC2, 0: OVC2 */ +#define USBPCTRL0_OVC1_VBUS1 BIT(9) /* Switches the OVC input pin for port 1: */ + /* 1: USB_OVC1, 0: OVC1/VBUS1 */ +#define USBPCTRL0_OVC0 BIT(8) /* Switches the OVC input pin for port 0: */ + /* 1: USB_OVC0 pin, 0: OVC0 */ +#define USBPCTRL0_OVC2_ACT BIT(6) /* Host mode: OVC2 polarity: */ + /* 1: active-high, 0: active-low */ + /* Function mode: be sure to set to 1 */ +#define USBPCTRL0_PENC BIT(4) /* Function mode: output level of PENC1 pin: */ + /* 1: high, 0: low */ +#define USBPCTRL0_OVC0_ACT BIT(3) /* Host mode: OVC0 polarity: */ + /* 1: active-high, 0: active-low */ +#define USBPCTRL0_OVC1_ACT BIT(1) /* Host mode: OVC1 polarity: */ + /* 1: active-high, 0: active-low */ + /* Function mode: be sure to set to 1 */ +#define USBPCTRL0_PORT1 BIT(0) /* Selects port 1 mode: */ + /* 1: function, 0: host */ + +struct rcar_phy_platform_data { + u32 usbpctrl0; /* USBPCTRL0 register value */ +}; + +#endif /* __RCAR_PHY_H */