From patchwork Thu May 30 08:52:40 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Magnus Damm X-Patchwork-Id: 2634101 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id E1289DF2A1 for ; Thu, 30 May 2013 08:45:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S967984Ab3E3IpX (ORCPT ); Thu, 30 May 2013 04:45:23 -0400 Received: from mail-pd0-f170.google.com ([209.85.192.170]:45621 "EHLO mail-pd0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S967915Ab3E3IpV (ORCPT ); Thu, 30 May 2013 04:45:21 -0400 Received: by mail-pd0-f170.google.com with SMTP id x10so10189092pdj.1 for ; Thu, 30 May 2013 01:45:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:date:message-id:in-reply-to:references:subject; bh=2hEWMTs9+Ada+kJOlQytBzsKX/9ha4DMe2ZGtkufCwM=; b=fFop9W6LuhCOkbQeLoqNeyJ5wQG6CcNB5oJL66FnhWLfYou0A7IjLRkUbOzGpz7lyu ayJULGSYBVKEH0/+xXFW267nOlm1jmuZgIJuO/Ii2bP2g2QmOC/lbtPoPofE8631GhxD KX0jK1N/ZhJ2dV7GYhUeNIg7bTKWZuV9IdqYA8wLywp/ZSSgQzF2QWMmGlc+2ZUXE+Vk i/rWRcw6dcc8NaRzo6MYwhD4hfbDac4fO3tWHwngKhgQVJ1pICfh6oDiuUonrUfhXsw6 66j5YG5n1g9kqNZeoHguJCXNNUwsbrVvYcRuU4t5yewoLNeqUPhEkYW7Ls+DHGgoI0Sw TVnw== X-Received: by 10.68.251.200 with SMTP id zm8mr6841445pbc.54.1369903521274; Thu, 30 May 2013 01:45:21 -0700 (PDT) Received: from [127.0.0.1] (49.14.32.202.bf.2iij.net. [202.32.14.49]) by mx.google.com with ESMTPSA id vv6sm43825913pab.6.2013.05.30.01.45.18 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 30 May 2013 01:45:20 -0700 (PDT) From: Magnus Damm To: linux-sh@vger.kernel.org Cc: arnd@arndb.de, horms@verge.net.au, ulrich.hecht@gmail.com, olof@lixom.net, Magnus Damm , linux-arm-kernel@lists.infradead.org Date: Thu, 30 May 2013 17:52:40 +0900 Message-Id: <20130530085240.24374.65991.sendpatchset@w520> In-Reply-To: <20130530085152.24374.64208.sendpatchset@w520> References: <20130530085152.24374.64208.sendpatchset@w520> Subject: [PATCH 05/05] ARM: shmobile: r8a73a4 CA7 setup arch timer Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org From: Magnus Damm Setup the CA7 arch timer in r8a73a4 at boot up. Thanks to Kevin Bracey at Renesas Mobile for initial implementation. We need to discuss if some of this can be moved into the common arch timer driver or not. It may also need to be shared with R-Car H2. So this is not ready for merge. Without this patch the interrupt count for the per-cpu arch timers for CA7 are stuck at zero. Not-yet-Signed-off-by: Magnus Damm --- arch/arm/mach-shmobile/smp-r8a73a4.c | 37 +++++++++++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html --- 0005/arch/arm/mach-shmobile/smp-r8a73a4.c +++ work/arch/arm/mach-shmobile/smp-r8a73a4.c 2013-05-30 17:13:01.000000000 +0900 @@ -50,6 +50,8 @@ #define CCI_SNOOP 0x0000 #define CCI_STATUS 0x000c +#define CNTFID0 0xe6080020 + static inline void r8a73a4_execute_wfe_as_nop(void) { unsigned int v; @@ -64,6 +66,32 @@ static inline void r8a73a4_execute_wfe_a : "cc"); } +static u32 r8a73a4_arch_freq; + +static inline void r8a73a4_reset_arch_timer(void) +{ + /* Program CNTFRQ from the frequency table */ + asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (r8a73a4_arch_freq)); + + /* CNTVOFF has to be initialized either from non-secure Hypervisor + * mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled + * then it should be handled by the secure code + */ + asm volatile( + "cps 0x16 @ Monitor mode" + "mrc p15, 0, r1, c1, c1, 0" + "orr r0, r1, #1 @ Set SCR.NS (non-secure)" + "mcr p15, 0, r0, c1, c1, 0" + "isb" + "mov r0, #0" + "mcrr p15, 4, r0, r0, c14 @ CNTVOFF" + "isb" + "mcr p15, 0, r1, c1, c1, 0 @ Restore SCR" + "isb" + "cps 0x13 @ Back to SVC mode" + : : : "r0", "r1"); +} + static void __init r8a73a4_smp_prepare_cpus(unsigned int max_cpus) { u32 bar; @@ -94,6 +122,11 @@ static void __init r8a73a4_smp_prepare_c /* wait for pending bit low */; iounmap(p); + /* Retrieve frequency to be able to later program CNTFRQ */ + p = ioremap_nocache(CNTFID0, 16); + r8a73a4_arch_freq = __raw_readl(p); + iounmap(p); + r8a73a4_execute_wfe_as_nop(); } @@ -115,9 +148,11 @@ static int __cpuinit r8a73a4_boot_second static void __cpuinit r8a73a4_secondary_init(unsigned int cpu) { - /* CA15 need SW workaround */ + /* CA15 and CA7 need SW workaround */ if (cpu_logical_map(cpu) < 4) r8a73a4_execute_wfe_as_nop(); + else + r8a73a4_reset_arch_timer(); } #ifdef CONFIG_HOTPLUG_CPU