From patchwork Thu Jun 12 09:42:24 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Magnus Damm X-Patchwork-Id: 4340161 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id D8ABF9F314 for ; Thu, 12 Jun 2014 09:40:22 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D5B5420328 for ; Thu, 12 Jun 2014 09:40:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D0C462025B for ; Thu, 12 Jun 2014 09:40:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932855AbaFLJkU (ORCPT ); Thu, 12 Jun 2014 05:40:20 -0400 Received: from mail-pb0-f54.google.com ([209.85.160.54]:40544 "EHLO mail-pb0-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932845AbaFLJkT (ORCPT ); Thu, 12 Jun 2014 05:40:19 -0400 Received: by mail-pb0-f54.google.com with SMTP id jt11so826383pbb.27 for ; Thu, 12 Jun 2014 02:40:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:date:message-id:in-reply-to:references:subject; bh=OEo68b7OS8wVDqou2Y+5zoyCZzk5iKLYEMNI/T7/l14=; b=j0F2YWTk/8F7Eq8E+YjABs4YUyLbCiY12gII2DhsHdxzRgwuY2f0OH3x7Qd9by4COO Je0VlV/Y0oxNbwGdBrOf0jWxvRjep2s8KPafJ8ZviSwijpnelin4WklwZKt5i6eap+wX g7Vl8wNDs5nrIqNOeGpqUq6lvkYtq4lw/qNpcZPPct9s/KS0qI9tfKhnuNjjaZEaZEqU MeF4Vf4YuPd+nrDt6wIBY9/l84GihQjScWHgmkKP95GssnprHrTDSiVYKMY7NCtGXkF9 rC+zdAxBF4zXia1XsdmqHnH4owncZUQ9cnkMW3/r12yge7yGKo7DHWPn8rpSWKLB6OtV K5+g== X-Received: by 10.66.66.225 with SMTP id i1mr19997907pat.0.1402566018918; Thu, 12 Jun 2014 02:40:18 -0700 (PDT) Received: from [127.0.0.1] (s214090.ppp.asahi-net.or.jp. [220.157.214.90]) by mx.google.com with ESMTPSA id lr3sm2673139pab.4.2014.06.12.02.40.17 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 12 Jun 2014 02:40:18 -0700 (PDT) From: Magnus Damm To: linux-sh@vger.kernel.org Cc: Magnus Damm , geert+renesas@glider.be Date: Thu, 12 Jun 2014 18:42:24 +0900 Message-Id: <20140612094224.4132.43639.sendpatchset@w520> In-Reply-To: <20140612094209.4132.78270.sendpatchset@w520> References: <20140612094209.4132.78270.sendpatchset@w520> Subject: [PATCH v2 02/07] DMA: shdma: 40-bit address prototype Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Magnus Damm Hack up 40-bit address support via the FIXSAR and FIXDAR addresses provided by the SYS-DMAC hardware in R-Car Gen2. The data sheet says that auto increment overflow from SAR to FIXSAR and DAR to FIXDAR does not happen, so based on that limit size of DMA transactions that try to cross the 32-bit boundary. Not for upstream merge. Signed-off-by: Magnus Damm --- Changes since V1: - Fix transfer length truncation calculation - thanks Geert! drivers/dma/sh/shdma.h | 4 ++-- drivers/dma/sh/shdmac.c | 46 ++++++++++++++++++++++++++++++++++++++++------ include/linux/sh_dma.h | 2 ++ 3 files changed, 44 insertions(+), 8 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html --- 0001/drivers/dma/sh/shdma.h +++ work/drivers/dma/sh/shdma.h 2014-06-10 23:10:51.000000000 +0900 @@ -46,8 +46,8 @@ struct sh_dmae_device { }; struct sh_dmae_regs { - u32 sar; /* SAR / source address */ - u32 dar; /* DAR / destination address */ + dma_addr_t sar; /* SAR / source address */ + dma_addr_t dar; /* DAR / destination address */ u32 tcr; /* TCR / transfer count */ }; --- 0001/drivers/dma/sh/shdmac.c +++ work/drivers/dma/sh/shdmac.c 2014-06-12 12:41:40.000000000 +0900 @@ -42,6 +42,8 @@ #define DAR 0x04 #define TCR 0x08 #define CHCR 0x0C +#define FIXSAR 0x10 +#define FIXDAR 0x14 #define DMAOR 0x40 #define TEND 0x18 /* USB-DMAC */ @@ -217,8 +219,16 @@ static u32 log2size_to_chcr(struct sh_dm static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw) { - sh_dmae_writel(sh_chan, hw->sar, SAR); - sh_dmae_writel(sh_chan, hw->dar, DAR); + struct sh_dmae_device *shdev = to_sh_dev(sh_chan); + +#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT + if (shdev->pdata->fourty_bits_addr) { + sh_dmae_writel(sh_chan, hw->sar >> 32, FIXSAR); + sh_dmae_writel(sh_chan, hw->dar >> 32, FIXDAR); + } +#endif + sh_dmae_writel(sh_chan, hw->sar & 0xffffffff, SAR); + sh_dmae_writel(sh_chan, hw->dar & 0xffffffff, DAR); sh_dmae_writel(sh_chan, hw->tcr >> sh_chan->xmit_shift, TCR); } @@ -290,9 +300,9 @@ static void sh_dmae_start_xfer(struct sh shdma_chan); struct sh_dmae_desc *sh_desc = container_of(sdesc, struct sh_dmae_desc, shdma_desc); - dev_dbg(sh_chan->shdma_chan.dev, "Queue #%d to %d: %u@%x -> %x\n", + dev_dbg(sh_chan->shdma_chan.dev, "Queue #%d to %d: %u@%pad-> %pad\n", sdesc->async_tx.cookie, sh_chan->shdma_chan.id, - sh_desc->hw.tcr, sh_desc->hw.sar, sh_desc->hw.dar); + sh_desc->hw.tcr, &sh_desc->hw.sar, &sh_desc->hw.dar); /* Get the ld start address from ld_queue */ dmae_set_reg(sh_chan, &sh_desc->hw); dmae_start(sh_chan); @@ -382,12 +392,28 @@ static int sh_dmae_desc_setup(struct shd struct shdma_desc *sdesc, dma_addr_t src, dma_addr_t dst, size_t *len) { + struct sh_dmae_chan *sh_chan = container_of(schan, + struct sh_dmae_chan, shdma_chan); struct sh_dmae_desc *sh_desc = container_of(sdesc, struct sh_dmae_desc, shdma_desc); + struct sh_dmae_device *shdev = to_sh_dev(sh_chan); if (*len > schan->max_xfer_len) *len = schan->max_xfer_len; +#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT + /* disable transfer across 32-bit boundary */ + if (shdev->pdata->fourty_bits_addr) { + dma_addr_t four_gigs = 1ULL << 32; + + if ((src >> 32) != ((src + *len - 1) >> 32)) + *len = four_gigs - (src & (four_gigs - 1)); + + if ((dst >> 32) != ((dst + *len - 1) >> 32)) + *len = four_gigs - (dst & (four_gigs - 1)); + } +#endif + sh_desc->hw.sar = src; sh_desc->hw.dar = dst; sh_desc->hw.tcr = *len; @@ -463,8 +489,16 @@ static bool sh_dmae_desc_completed(struc struct sh_dmae_chan, shdma_chan); struct sh_dmae_desc *sh_desc = container_of(sdesc, struct sh_dmae_desc, shdma_desc); - u32 sar_buf = sh_dmae_readl(sh_chan, SAR); - u32 dar_buf = sh_dmae_readl(sh_chan, DAR); + struct sh_dmae_device *shdev = to_sh_dev(sh_chan); + dma_addr_t sar_buf = sh_dmae_readl(sh_chan, SAR); + dma_addr_t dar_buf = sh_dmae_readl(sh_chan, DAR); + +#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT + if (shdev->pdata->fourty_bits_addr) { + sar_buf |= (dma_addr_t)sh_dmae_readl(sh_chan, FIXSAR) << 32; + dar_buf |= (dma_addr_t)sh_dmae_readl(sh_chan, FIXDAR) << 32; + } +#endif return (sdesc->direction == DMA_DEV_TO_MEM && (sh_desc->hw.dar + sh_desc->hw.tcr) == dar_buf) || --- 0001/include/linux/sh_dma.h +++ work/include/linux/sh_dma.h 2014-06-10 23:10:51.000000000 +0900 @@ -70,6 +70,7 @@ struct sh_dmae_channel { * @chclr_present: DMAC has one or several CHCLR registers * @chclr_bitwise: channel CHCLR registers are bitwise * @slave_only: DMAC cannot be used for MEMCPY + * @fourty_bits_addr: Hardware support dealing with 40 bit addresses */ struct sh_dmae_pdata { const struct sh_dmae_slave_config *slave; @@ -92,6 +93,7 @@ struct sh_dmae_pdata { unsigned int chclr_present:1; unsigned int chclr_bitwise:1; unsigned int slave_only:1; + unsigned int fourty_bits_addr:1; }; /* DMAOR definitions */