From patchwork Wed Dec 3 12:18:03 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Magnus Damm X-Patchwork-Id: 5430281 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 657B7BEEA8 for ; Wed, 3 Dec 2014 12:16:35 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5F1852028D for ; Wed, 3 Dec 2014 12:16:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2C52820256 for ; Wed, 3 Dec 2014 12:16:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752326AbaLCMP3 (ORCPT ); Wed, 3 Dec 2014 07:15:29 -0500 Received: from mail-pa0-f49.google.com ([209.85.220.49]:54669 "EHLO mail-pa0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752790AbaLCMPZ (ORCPT ); Wed, 3 Dec 2014 07:15:25 -0500 Received: by mail-pa0-f49.google.com with SMTP id eu11so15429349pac.8 for ; Wed, 03 Dec 2014 04:15:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:date:message-id:in-reply-to:references:subject; bh=5SifPA7LCvNQQM8hVe/oHvLw2c/5kZRZWjD1M2hizVs=; b=jOdSm5E2SA8fCq4mfrBHub+QnWvOmNfgmSUPudu3so5pYqUjVlkQzvRRKaA/FrtWlX AMzLWhzytsZnRv0sNLJ1TMBwLZC0n/tLVMXMnQFP0h/TaXe391nYBRxXCs/niJpUpgXh o+lImMLN+zIu0F2BGANM1Bmt/2pTpq8A4tTvnWLrEKVRj24t8TJHWUoTCTZN7698iyMI K7a8op+SjZk63/ym7+Fd6S63uMUrvl4jySjoxNoMEcXjY+IldBH2yrmJ+jCp2te2Q5u4 BrY8BHtCWEF0fipBOWlrOAEW69Ou6O5f9kKFG+WdNOptEttRXESSRgMjUN/TTO6BVWgN S/ng== X-Received: by 10.68.245.7 with SMTP id xk7mr15181854pbc.65.1417608924323; Wed, 03 Dec 2014 04:15:24 -0800 (PST) Received: from [127.0.0.1] (s214090.ppp.asahi-net.or.jp. [220.157.214.90]) by mx.google.com with ESMTPSA id w1sm6021278pdf.38.2014.12.03.04.15.21 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 03 Dec 2014 04:15:23 -0800 (PST) From: Magnus Damm To: Magnus Damm , linux-sh@vger.kernel.org Cc: Magnus Damm , horms@verge.net.au, tglx@linutronix.de, jason@lakedaemon.net, linux-kernel@vger.kernel.org Date: Wed, 03 Dec 2014 21:18:03 +0900 Message-Id: <20141203121803.5936.35881.sendpatchset@w520> In-Reply-To: <20141203121753.5936.36253.sendpatchset@w520> References: <20141203121753.5936.36253.sendpatchset@w520> Subject: [PATCH 01/02] irqchip: renesas-intc-irqpin: r8a7779 IRLM setup support Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Magnus Damm Add r8a7779 specific support for IRLM bit configuration in the INTC-IRQPIN driver. Without this code we need special workaround code in arch/arm/mach-shmobile. The IRLM bit for the INTC hardware exists on various older SH-based SoCs and is used to select between two modes for the external interrupt pins IRQ0 to IRQ3: IRLM = 0: (default from reset on r8a7779) In this mode the pins IRQ0 to IRQ3 are used together to give a value between 0 and 15 to the SoC. External logic is required for masking. This mode is not supported by the INTC-IRQPIN driver. IRLM = 1: (needs this patch or configuration elsewhere) In this mode IRQ0 to IRQ3 operate as 4 individual external interrupt pins. In this mode the SMSC ethernet chip can be used via IRQ1 on r8a7779 Marzen. This mode is the only supported mode by the INTC-IRQPIN driver. For this patch to work the r8a7779 DTS needs to pass the ICR0 register as the last register bank. Signed-off-by: Magnus Damm --- Written against renesas-devel-20141202-v3.18-rc7 which is basically v3.18-rc7 plus latest arch/arm/mach-shmobile code. Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt | 5 + drivers/irqchip/irq-renesas-intc-irqpin.c | 50 ++++++++-- 2 files changed, 46 insertions(+), 9 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html --- 0001/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt +++ work/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt 2014-12-03 20:25:13.000000000 +0900 @@ -9,6 +9,11 @@ Required properties: - "renesas,intc-irqpin-r8a7778" (R-Car M1A) - "renesas,intc-irqpin-r8a7779" (R-Car H1) - "renesas,intc-irqpin-sh73a0" (SH-Mobile AG5) + +- reg: Base address and length of each register bank used by the external + IRQ pins driven by the interrupt controller hardware module. The base + addresses, length and number of required register banks varies with soctype. + - #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in interrupts.txt in this directory --- 0001/drivers/irqchip/irq-renesas-intc-irqpin.c +++ work/drivers/irqchip/irq-renesas-intc-irqpin.c 2014-12-03 20:32:59.000000000 +0900 @@ -30,6 +30,7 @@ #include #include #include +#include #include #include @@ -40,7 +41,9 @@ #define INTC_IRQPIN_REG_SOURCE 2 /* INTREQnn */ #define INTC_IRQPIN_REG_MASK 3 /* INTMSKnn */ #define INTC_IRQPIN_REG_CLEAR 4 /* INTMSKCLRnn */ -#define INTC_IRQPIN_REG_NR 5 +#define INTC_IRQPIN_REG_NR_MANDATORY 5 +#define INTC_IRQPIN_REG_IRLM 5 /* ICR0 with IRLM bit (optional) */ +#define INTC_IRQPIN_REG_NR 6 /* INTC external IRQ PIN hardware register access: * @@ -82,6 +85,10 @@ struct intc_irqpin_priv { u8 shared_irq_mask; }; +struct intc_irqpin_irlm_config { + unsigned int irlm_bit; +}; + static unsigned long intc_irqpin_read32(void __iomem *iomem) { return ioread32(iomem); @@ -345,10 +352,23 @@ static struct irq_domain_ops intc_irqpin .xlate = irq_domain_xlate_twocell, }; +static const struct intc_irqpin_irlm_config intc_irqpin_irlm_r8a7779 = { + .irlm_bit = 23, /* ICR0.IRLM0 */ +}; + +static const struct of_device_id intc_irqpin_dt_ids[] = { + { .compatible = "renesas,intc-irqpin", }, + { .compatible = "renesas,intc-irqpin-r8a7779", + .data = &intc_irqpin_irlm_r8a7779 }, + {}, +}; +MODULE_DEVICE_TABLE(of, intc_irqpin_dt_ids); + static int intc_irqpin_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct renesas_intc_irqpin_config *pdata = dev->platform_data; + const struct of_device_id *of_id; struct intc_irqpin_priv *p; struct intc_irqpin_iomem *i; struct resource *io[INTC_IRQPIN_REG_NR]; @@ -391,10 +411,11 @@ static int intc_irqpin_probe(struct plat pm_runtime_enable(dev); pm_runtime_get_sync(dev); - /* get hold of manadatory IOMEM */ + /* get hold of register banks */ + memset(io, 0, sizeof(io)); for (k = 0; k < INTC_IRQPIN_REG_NR; k++) { io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k); - if (!io[k]) { + if (!io[k] && k < INTC_IRQPIN_REG_NR_MANDATORY) { dev_err(dev, "not enough IOMEM resources\n"); ret = -EINVAL; goto err0; @@ -422,6 +443,10 @@ static int intc_irqpin_probe(struct plat for (k = 0; k < INTC_IRQPIN_REG_NR; k++) { i = &p->iomem[k]; + /* handle optional registers */ + if (!io[k]) + continue; + switch (resource_size(io[k])) { case 1: i->width = 8; @@ -448,6 +473,19 @@ static int intc_irqpin_probe(struct plat } } + /* configure "individual IRQ mode" where needed */ + of_id = of_match_device(intc_irqpin_dt_ids, dev); + if (of_id && of_id->data) { + const struct intc_irqpin_irlm_config *irlm_config = of_id->data; + + if (io[INTC_IRQPIN_REG_IRLM]) + intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_IRLM, + irlm_config->irlm_bit, + 1, 1); + else + dev_warn(dev, "unable to select IRLM mode\n"); + } + /* mask all interrupts using priority */ for (k = 0; k < p->number_of_irqs; k++) intc_irqpin_mask_unmask_prio(p, k, 1); @@ -550,12 +588,6 @@ static int intc_irqpin_remove(struct pla return 0; } -static const struct of_device_id intc_irqpin_dt_ids[] = { - { .compatible = "renesas,intc-irqpin", }, - {}, -}; -MODULE_DEVICE_TABLE(of, intc_irqpin_dt_ids); - static struct platform_driver intc_irqpin_device_driver = { .probe = intc_irqpin_probe, .remove = intc_irqpin_remove,