From patchwork Tue Mar 17 01:36:18 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Magnus Damm X-Patchwork-Id: 6026931 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 403A8BF90F for ; Tue, 17 Mar 2015 01:35:29 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3DBC02045A for ; Tue, 17 Mar 2015 01:35:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4ACB72045E for ; Tue, 17 Mar 2015 01:35:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751944AbbCQBf0 (ORCPT ); Mon, 16 Mar 2015 21:35:26 -0400 Received: from mail-pd0-f181.google.com ([209.85.192.181]:35579 "EHLO mail-pd0-f181.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750950AbbCQBf0 (ORCPT ); Mon, 16 Mar 2015 21:35:26 -0400 Received: by pdbop1 with SMTP id op1so74341662pdb.2 for ; Mon, 16 Mar 2015 18:35:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:date:message-id:subject; bh=9HnejA/ngoxITvykTMBK1n58vX//zRTGFN6pBEDOlf4=; b=dsC38XWkxIBNIIVbPbNA4vfknnbX37tD5JahPPYvR+nFbwNX3kYFG2DA0I0Vreh998 RTmmLXyDUxeu39voXsKgPsQGIbWP7mp7qxj5MGVsWMQEuF0enHeY7p4An0+3UifuN/Te FkvrWFOsWKPRo+x6G8CbxTaFTXR6mO0FfNC4lN+RunNSmqhxq35wyEBphAX1u0KStI6j iIvcAqkqItNs+AhHMG0uRGBWZiPFk+M/KEJ05NTs1pM7sG6zZkiWyQAEe1otW1gf1Y/I IGHJr8ZdrRE5uQ4gHgd1fVXhe+0eTvFQXFGGiZaFEaUIdjpf8Y4xkbWRl3o5wf8/YI0r 7UJw== X-Received: by 10.67.10.47 with SMTP id dx15mr145701738pad.139.1426556125677; Mon, 16 Mar 2015 18:35:25 -0700 (PDT) Received: from [127.0.0.1] (s214090.ppp.asahi-net.or.jp. [220.157.214.90]) by mx.google.com with ESMTPSA id g11sm19369910pat.24.2015.03.16.18.35.23 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Mar 2015 18:35:24 -0700 (PDT) From: Magnus Damm To: linux-sh@vger.kernel.org Cc: Magnus Damm Date: Tue, 17 Mar 2015 10:36:18 +0900 Message-Id: <20150317013618.3502.75273.sendpatchset@little-apple> Subject: [PATCH] drm/rcar-du: Lager DU2 VGA hack Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Magnus Damm This is a very short term hack that separates VGA and HDMI on r8a7790 Lager. It does that by forcing VGA on DU2 and keeping LVDS2 as DU0 and putting HDMI(LVDS1) to DU1 only. The idea is that separating VGA@DU2 from HDMI@DU1/LVDS@DU0 should reduce the need to flicker. DU2 is independent from DU1 and DU0 and the patch does improve the state since with it applied changing the VGA mode does not affect HDMI at all. It may make more sense to adjust the code to allocate the planes in a better way to avoid flicker completely. This patch needs to be reworked as it does not apply to -next, it is posted only as proof of concept. Not for upstream merge. Two random observations: 1) The dpad0_source bits in the current driver needs more work. Unless I hard code "2" as index the setmode test image never reaches the display, however fbcon works without it. 2) It looks like the LVDS quirk stuff only applies to DU0/DU1 and not to DU2. At least the colors look completely wrong if the quirk is enabled when DU2 is used. Not-Yet-Signed-off-by: Magnus Damm --- drivers/gpu/drm/rcar-du/rcar_du_drv.c | 4 ++-- drivers/gpu/drm/rcar-du/rcar_du_group.c | 14 ++++++-------- drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c | 3 ++- 3 files changed, 10 insertions(+), 11 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html --- 0001/drivers/gpu/drm/rcar-du/rcar_du_drv.c +++ work/drivers/gpu/drm/rcar-du/rcar_du_drv.c 2015-03-16 11:15:56.467702953 +0900 @@ -65,7 +65,7 @@ static const struct rcar_du_device_info * (currently unsupported) TCON output. */ [RCAR_DU_OUTPUT_DPAD0] = { - .possible_crtcs = BIT(2) | BIT(1) | BIT(0), + .possible_crtcs = BIT(2), .encoder_type = DRM_MODE_ENCODER_NONE, .port = 0, }, @@ -75,7 +75,7 @@ static const struct rcar_du_device_info .port = 1, }, [RCAR_DU_OUTPUT_LVDS1] = { - .possible_crtcs = BIT(2) | BIT(1), + .possible_crtcs = BIT(1), .encoder_type = DRM_MODE_ENCODER_LVDS, .port = 2, }, --- 0001/drivers/gpu/drm/rcar-du/rcar_du_group.c +++ work/drivers/gpu/drm/rcar-du/rcar_du_group.c 2015-03-16 12:18:20.137689500 +0900 @@ -52,7 +52,7 @@ static void rcar_du_group_setup_defr8(st * routing to DPAD0 */ if (rgrp->index == 0) - defr8 |= DEFR8_DRGBS_DU(rgrp->dev->dpad0_source); + defr8 |= DEFR8_DRGBS_DU(2/*rgrp->dev->dpad0_source*/); rcar_du_group_write(rgrp, DEFR8, defr8); } @@ -67,8 +67,6 @@ static void rcar_du_group_setup(struct r rcar_du_group_write(rgrp, DEFR5, DEFR5_CODE | DEFR5_DEFE5); if (rcar_du_has(rgrp->dev, RCAR_DU_FEATURE_EXT_CTRL_REGS)) { - rcar_du_group_setup_defr8(rgrp); - /* Configure input dot clock routing. We currently hardcode the * configuration to routing DOTCLKINn to DUn. */ @@ -80,11 +78,6 @@ static void rcar_du_group_setup(struct r DIDSR_PDCS_CLK(1, 0) | DIDSR_PDCS_CLK(0, 0)); } - - /* Use DS1PR and DS2PR to configure planes priorities and connects the - * superposition 0 to DU0 pins. DU1 pins will be configured dynamically. - */ - rcar_du_group_write(rgrp, DORCR, DORCR_PG1D_DS1 | DORCR_DPRS); } /* @@ -194,6 +187,11 @@ int rcar_du_group_set_routing(struct rca else dorcr |= DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_DS2; + /* Use DS1PR and DS2PR to configure planes priorities and connects the + * superposition 0 to DU0 pins. DU1 pins are configured dynamically. + */ + dorcr |= DORCR_PG1D_DS1 | DORCR_DPRS; + rcar_du_group_write(rgrp, DORCR, dorcr); return rcar_du_set_dpad0_routing(rgrp->dev); --- 0001/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c +++ work/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c 2015-03-16 12:23:25.807688401 +0900 @@ -78,7 +78,8 @@ static int rcar_du_lvdsenc_start(struct LVDCTRCR_CTR2SEL_DISP | LVDCTRCR_CTR1SEL_VSYNC | LVDCTRCR_CTR0SEL_HSYNC); - if (rcar_du_needs(lvds->dev, RCAR_DU_QUIRK_LVDS_LANES)) + if (rcrtc->index != 2 && + rcar_du_needs(lvds->dev, RCAR_DU_QUIRK_LVDS_LANES)) lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 3) | LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 1); else