From patchwork Thu Mar 19 01:50:13 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Magnus Damm X-Patchwork-Id: 6045101 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id DFE819F314 for ; Thu, 19 Mar 2015 01:49:22 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CACE320376 for ; Thu, 19 Mar 2015 01:49:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C89AE20364 for ; Thu, 19 Mar 2015 01:49:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755066AbbCSBtU (ORCPT ); Wed, 18 Mar 2015 21:49:20 -0400 Received: from mail-pd0-f172.google.com ([209.85.192.172]:34258 "EHLO mail-pd0-f172.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750839AbbCSBtT (ORCPT ); Wed, 18 Mar 2015 21:49:19 -0400 Received: by pdbni2 with SMTP id ni2so60261272pdb.1; Wed, 18 Mar 2015 18:49:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:date:message-id:in-reply-to:references:subject; bh=r/AlpSpTVZO/+v5oqcF2GypGdwXvrdSNFkaEyl1213I=; b=Ed+2bZmEE6NRfsRm8MtppaJnQT4Fw5qtUdVp4koD70LQ6MOv27nPmu5T5wQbuxOSwE O7JTU5+lv0zwnjFcdPxXQ06dGhnbQoiB4MiT91PnXD7KWca+9zz7WwmQpRliiHK2u50U bMXeI+yrdHI4naXK2oyTRy7Mwkxv7aQabbXUrOtBxDXBW1QFiNJKr9Zdsc+nF3PfZ3BW LrknruAmJmkgYCucl1rYmNs3tpmk0A7yExnm+JANWkXXVHjfkOoyoMyCg+cyx7PALoNP QHlomY2GFkMGg7G6lrn42sa0cidtFjd26+MGW+hCv14EF/Q/14ctCn9xFROqtatYh/cG yHaA== X-Received: by 10.66.123.110 with SMTP id lz14mr73883449pab.30.1426729759178; Wed, 18 Mar 2015 18:49:19 -0700 (PDT) Received: from [127.0.0.1] (s214090.ppp.asahi-net.or.jp. [220.157.214.90]) by mx.google.com with ESMTPSA id g11sm29736323pat.24.2015.03.18.18.49.16 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 18 Mar 2015 18:49:18 -0700 (PDT) From: Magnus Damm To: linux-sh@vger.kernel.org Cc: gregkh@linuxfoundation.org, geert@glider.be, laurent.pinchart@ideasonboard.com, linux-serial@vger.kernel.org, Magnus Damm , jslaby@suse.cz Date: Thu, 19 Mar 2015 10:50:13 +0900 Message-Id: <20150319015013.14235.74159.sendpatchset@little-apple> In-Reply-To: <20150319014933.14235.44835.sendpatchset@little-apple> References: <20150319014933.14235.44835.sendpatchset@little-apple> Subject: [PATCH v2 04/05] serial: sh-sci: Add SCIFA/SCIFB CTS/RTS pin setup Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Magnus Damm Add SCIFA/SCIFB pin setup code for CTS/RTS pins to handle both cases of hardware flow control enabled or disabled. Signed-off-by: Magnus Damm --- Changes since V1: - Adjusted function name to match with suggestion from Laurent - Added bit definitions for SCPCR and SCPDR - When modem control is disabled, set RTS to zero to keep it asserted. drivers/tty/serial/sh-sci.c | 59 ++++++++++++++++++++++++++++++++++++++++++- include/linux/serial_sci.h | 9 ++++++ 2 files changed, 67 insertions(+), 1 deletion(-) -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html --- 0004/drivers/tty/serial/sh-sci.c +++ work/drivers/tty/serial/sh-sci.c 2015-03-19 09:39:11.836792354 +0900 @@ -168,6 +168,8 @@ static struct plat_sci_reg sci_regmap[SC [SCSPTR] = sci_reg_invalid, [SCLSR] = sci_reg_invalid, [HSSRR] = sci_reg_invalid, + [SCPCR] = sci_reg_invalid, + [SCPDR] = sci_reg_invalid, }, /* @@ -188,6 +190,8 @@ static struct plat_sci_reg sci_regmap[SC [SCSPTR] = sci_reg_invalid, [SCLSR] = sci_reg_invalid, [HSSRR] = sci_reg_invalid, + [SCPCR] = sci_reg_invalid, + [SCPDR] = sci_reg_invalid, }, /* @@ -207,6 +211,8 @@ static struct plat_sci_reg sci_regmap[SC [SCSPTR] = sci_reg_invalid, [SCLSR] = sci_reg_invalid, [HSSRR] = sci_reg_invalid, + [SCPCR] = { 0x30, 16 }, + [SCPDR] = { 0x34, 16 }, }, /* @@ -226,6 +232,8 @@ static struct plat_sci_reg sci_regmap[SC [SCSPTR] = sci_reg_invalid, [SCLSR] = sci_reg_invalid, [HSSRR] = sci_reg_invalid, + [SCPCR] = { 0x30, 16 }, + [SCPDR] = { 0x34, 16 }, }, /* @@ -246,6 +254,8 @@ static struct plat_sci_reg sci_regmap[SC [SCSPTR] = { 0x20, 16 }, [SCLSR] = { 0x24, 16 }, [HSSRR] = sci_reg_invalid, + [SCPCR] = sci_reg_invalid, + [SCPDR] = sci_reg_invalid, }, /* @@ -265,6 +275,8 @@ static struct plat_sci_reg sci_regmap[SC [SCSPTR] = sci_reg_invalid, [SCLSR] = sci_reg_invalid, [HSSRR] = sci_reg_invalid, + [SCPCR] = sci_reg_invalid, + [SCPDR] = sci_reg_invalid, }, /* @@ -284,6 +296,8 @@ static struct plat_sci_reg sci_regmap[SC [SCSPTR] = { 0x20, 16 }, [SCLSR] = { 0x24, 16 }, [HSSRR] = sci_reg_invalid, + [SCPCR] = sci_reg_invalid, + [SCPDR] = sci_reg_invalid, }, /* @@ -303,6 +317,8 @@ static struct plat_sci_reg sci_regmap[SC [SCSPTR] = { 0x20, 16 }, [SCLSR] = { 0x24, 16 }, [HSSRR] = { 0x40, 16 }, + [SCPCR] = sci_reg_invalid, + [SCPDR] = sci_reg_invalid, }, /* @@ -323,6 +339,8 @@ static struct plat_sci_reg sci_regmap[SC [SCSPTR] = sci_reg_invalid, [SCLSR] = { 0x24, 16 }, [HSSRR] = sci_reg_invalid, + [SCPCR] = sci_reg_invalid, + [SCPDR] = sci_reg_invalid, }, /* @@ -343,6 +361,8 @@ static struct plat_sci_reg sci_regmap[SC [SCSPTR] = { 0x24, 16 }, [SCLSR] = { 0x28, 16 }, [HSSRR] = sci_reg_invalid, + [SCPCR] = sci_reg_invalid, + [SCPDR] = sci_reg_invalid, }, /* @@ -363,6 +383,8 @@ static struct plat_sci_reg sci_regmap[SC [SCSPTR] = sci_reg_invalid, [SCLSR] = sci_reg_invalid, [HSSRR] = sci_reg_invalid, + [SCPCR] = sci_reg_invalid, + [SCPDR] = sci_reg_invalid, }, }; @@ -542,6 +564,34 @@ static void sci_init_ctsrts_default(stru serial_port_out(port, SCSPTR, status); /* Set RTS = 0 */ } +static void sci_init_ctsrts_scifab(struct uart_port *port, bool hwflow_enabled) +{ + unsigned short control, data; + + /* SCIFA/SCIFB CTS/RTS pin configuration depends on user space. + * + * In case of CTS - (SCPDR.CTSD is always accessible): + * - Hardware flow control enabled: "CTS pin function" + * - Hardware flow control disabled: "Input port" + * + * In case of RTS: + * - Hardware flow control enabled: "RTS pin function" + * - Hardware flow control disabled: "Output port" with value 0 + */ + control = serial_port_in(port, SCPCR); + data = serial_port_in(port, SCPDR); + + if (hwflow_enabled) { + control &= ~(SCPCR_RTSC | SCPCR_CTSC); + } else { + control |= SCPCR_RTSC | SCPCR_CTSC; + data &= ~SCPDR_RTSD; + } + + serial_port_out(port, SCPDR, data); + serial_port_out(port, SCPCR, control); +} + static void sci_init_pins(struct uart_port *port, unsigned int cflag) { struct sci_port *s = to_sci_port(port); @@ -568,7 +618,14 @@ static void sci_init_pins(struct uart_po if (!(s->cfg->capabilities & SCIx_HAVE_RTSCTS)) return; - sci_init_ctsrts_default(port, hwflow_enabled); + switch (s->cfg->type) { + case PORT_SCIFA: + case PORT_SCIFB: + sci_init_ctsrts_scifab(port, hwflow_enabled); + break; + default: + sci_init_ctsrts_default(port, hwflow_enabled); + } } static int sci_txfill(struct uart_port *port) --- 0004/include/linux/serial_sci.h +++ work/include/linux/serial_sci.h 2015-03-19 09:41:09.116791933 +0900 @@ -66,6 +66,13 @@ /* HSSRR HSCIF */ #define HSCIF_SRE 0x8000 /* Sampling Rate Register Enable */ +/* SCPCR (Serial Port Control Register) */ +#define SCPCR_RTSC (1 << 4) /* Serial Port RTS Pin / Output Pin */ +#define SCPCR_CTSC (1 << 3) /* Serial Port CTS Pin / Input Pin */ + +/* SCPDR (Serial Port Data Register) */ +#define SCPDR_RTSD (1 << 4) /* Serial Port RTS Output Pin Data */ + enum { SCIx_PROBE_REGTYPE, @@ -102,6 +109,8 @@ enum { SCRFDR, /* Receive FIFO Data Count Register */ SCSPTR, /* Serial Port Register */ HSSRR, /* Sampling Rate Register */ + SCPCR, /* Serial Port Control Register */ + SCPDR, /* Serial Port Data Register */ SCIx_NR_REGS, };