From patchwork Thu Jun 18 18:45:18 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Michael_B=C3=BCsch?= X-Patchwork-Id: 6640231 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 2DCB0C0020 for ; Thu, 18 Jun 2015 19:23:47 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8D6D1206FC for ; Thu, 18 Jun 2015 19:23:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D28DD206D2 for ; Thu, 18 Jun 2015 19:23:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756290AbbFRTXp (ORCPT ); Thu, 18 Jun 2015 15:23:45 -0400 Received: from bues.ch ([80.190.117.144]:33907 "EHLO bues.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755835AbbFRTXm (ORCPT ); Thu, 18 Jun 2015 15:23:42 -0400 Received: by bues.ch with esmtpsa (Exim 4.80) (envelope-from ) id 1Z5epJ-0000tN-Hb; Thu, 18 Jun 2015 20:46:13 +0200 Date: Thu, 18 Jun 2015 20:45:18 +0200 From: Michael =?UTF-8?B?QsO8c2No?= To: linux-sh@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ilia Mirkin Subject: [PATCH] m32r: Fix clearing of thread info fault code Message-ID: <20150618204518.02c852e0@wiggum> X-Mailer: Claws Mail 3.11.1 (GTK+ 2.24.28; x86_64-pc-linux-gnu) MIME-Version: 1.0 Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-7.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_TVD_MIME_EPI, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The expression (~0 >> x) will always yield all-ones, because the right shift is an arithmetic right shift that will always shift ones in. Hence the old fault code bits will not be cleared before being ORed with the new fault code. Fix this by forcing a logical right shift instead of an arithmetic right shift by using an unsigned long constant. Reported-by: Ilia Mirkin Signed-off-by: Michael Buesch --- The code also assumes sizeof(ti->flags) == 4. But that probably is ok for this arch. This patch is untested, because I do not have the hardware. Index: linux/arch/m32r/include/asm/thread_info.h =================================================================== --- linux.orig/arch/m32r/include/asm/thread_info.h +++ linux/arch/m32r/include/asm/thread_info.h @@ -77,7 +77,7 @@ static inline struct thread_info *curren static inline void set_thread_fault_code(unsigned int val) { struct thread_info *ti = current_thread_info(); - ti->flags = (ti->flags & (~0 >> (32 - TI_FLAG_FAULT_CODE_SHIFT))) + ti->flags = (ti->flags & (~0UL >> (32 - TI_FLAG_FAULT_CODE_SHIFT))) | (val << TI_FLAG_FAULT_CODE_SHIFT); }