From patchwork Mon Aug 31 06:29:30 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Magnus Damm X-Patchwork-Id: 7098531 X-Patchwork-Delegate: horms@verge.net.au Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 4B3BE9F36E for ; Mon, 31 Aug 2015 06:25:22 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 365E720872 for ; Mon, 31 Aug 2015 06:25:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 219DD20871 for ; Mon, 31 Aug 2015 06:25:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751702AbbHaGZT (ORCPT ); Mon, 31 Aug 2015 02:25:19 -0400 Received: from mail-pa0-f50.google.com ([209.85.220.50]:36476 "EHLO mail-pa0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750912AbbHaGZS (ORCPT ); Mon, 31 Aug 2015 02:25:18 -0400 Received: by pacrd3 with SMTP id rd3so12330102pac.3 for ; Sun, 30 Aug 2015 23:25:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:date:message-id:in-reply-to:references:subject; bh=5MQ7Xibcw1YM+K3z4aAIkFmsqFSvWItpv8DrBB0K5vs=; b=Jj72kfY1kzNaaax3sejm7anC3cY5kOFGuzlkobfRZPdQRfn+X9bJR5HPiAbqkX5+mf XH9eMlH7o3thhNU5wcimiV7n/zqsoFGl2yUV+/wXQ9K8xxp3+xtC2lNqQT62oUS4yNhC jhlIITRe7uJc4Wr0YPUAnGaVmjxRW054Soglmf7GgXxITzmChIxhCSOcwudDpQ5+7Hy2 BA2Hbv0O3rXiC5tcxcOnaA551UaLvUDYcpB7jXP68DzX45j5QvrOK5qINDjhMrXDKLh7 iohFFiEuN+ehG3/qI0mL11VC2Rs8QVcDwApCwfAZ3nJKCqmURbnWdeWihDHQ7/BxhgbP H+HQ== X-Received: by 10.68.134.169 with SMTP id pl9mr34868729pbb.164.1441002318535; Sun, 30 Aug 2015 23:25:18 -0700 (PDT) Received: from [127.0.0.1] (s214090.ppp.asahi-net.or.jp. [220.157.214.90]) by smtp.gmail.com with ESMTPSA id tz1sm13155637pbc.50.2015.08.30.23.25.14 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 30 Aug 2015 23:25:16 -0700 (PDT) From: Magnus Damm To: Magnus Damm , linux-sh@vger.kernel.org Cc: takeshi.kihara.df@renesas.com, kuninori.morimoto.gx@renesas.com, gaku.inami.xw@bp.renesas.com, yoshihiro.shimoda.uh@renesas.com, hisao.munakata.vt@renesas.com, toshiaki.komatsu.ud@renesas.com, yusuke.goda.sx@renesas.com, horms@verge.net.au, geert@linux-m68k.org, laurent.pinchart@ideasonboard.com, Magnus Damm , yoshiyuki.ito.ub@renesas.com Date: Mon, 31 Aug 2015 15:29:30 +0900 Message-Id: <20150831062930.24004.93722.sendpatchset@little-apple> In-Reply-To: <20150831062907.24004.79614.sendpatchset@little-apple> References: <20150831062907.24004.79614.sendpatchset@little-apple> Subject: [PATCH v8 02/07] arm64: renesas: r8a7795 dtsi: Add all common divider clocks Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Geert Uytterhoeven Add all clocks generated from PLL1 by the CPG common divider block. This includes s3d4, which was modelled as a direct child from pll1 before. Signed-off-by: Geert Uytterhoeven Signed-off-by: Magnus Damm --- Based on: [PATCH 3/3] arm64: renesas: r8a7795 dtsi: Add all common divider clocks Changes: (Magnus Damm ) - Folded in s3d4_clk - Reordered to apply without SCIF bits arch/arm64/boot/dts/renesas/r8a7795.dtsi | 160 ++++++++++++++++++++++++++++++ 1 file changed, 160 insertions(+) -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html --- 0012/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ work/arch/arm64/boot/dts/renesas/r8a7795.dtsi 2015-08-29 17:10:36.532366518 +0900 @@ -70,6 +70,166 @@ #clock-cells = <1>; ranges; + zt_clk: zt { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7795_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + }; + + ztr_clk: ztr { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7795_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <6>; + clock-mult = <1>; + }; + + ztrd2_clk: ztrd2 { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7795_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <12>; + clock-mult = <1>; + }; + + zx_clk: zx { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7795_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + + s0_clk: s0 { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7795_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + + s0d1_clk: s0d1 { + compatible = "fixed-factor-clock"; + clocks = <&s0_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + + s0d4_clk: s0d4 { + compatible = "fixed-factor-clock"; + clocks = <&s0_clk>; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + }; + + s1_clk: s1 { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7795_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <3>; + clock-mult = <1>; + }; + + s1d1_clk: s1d1 { + compatible = "fixed-factor-clock"; + clocks = <&s1_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + + s1d2_clk: s1d2 { + compatible = "fixed-factor-clock"; + clocks = <&s1_clk>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + + s1d4_clk: s1d4 { + compatible = "fixed-factor-clock"; + clocks = <&s1_clk>; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + }; + + s2_clk: s2 { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7795_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + }; + + s2d1_clk: s2d1 { + compatible = "fixed-factor-clock"; + clocks = <&s2_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + + s2d2_clk: s2d2 { + compatible = "fixed-factor-clock"; + clocks = <&s2_clk>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + + s2d4_clk: s2d4 { + compatible = "fixed-factor-clock"; + clocks = <&s2_clk>; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + }; + + s3_clk: s3 { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7795_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <6>; + clock-mult = <1>; + }; + + s3d1_clk: s3d1 { + compatible = "fixed-factor-clock"; + clocks = <&s3_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + + s3d2_clk: s3d2 { + compatible = "fixed-factor-clock"; + clocks = <&s3_clk>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + + s3d4_clk: s3d4 { + compatible = "fixed-factor-clock"; + clocks = <&s3_clk>; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + }; + + cl_clk: cl { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7795_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <48>; + clock-mult = <1>; + }; + cpg_clocks: cpg_clocks@e6150000 { compatible = "renesas,r8a7795-cpg-clocks", "renesas,rcar-gen3-cpg-clocks";