From patchwork Mon Sep 7 16:33:46 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Magnus Damm X-Patchwork-Id: 7137361 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id C7D3D9F314 for ; Mon, 7 Sep 2015 16:29:28 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DCA5220610 for ; Mon, 7 Sep 2015 16:29:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E58FF2060B for ; Mon, 7 Sep 2015 16:29:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753193AbbIGQ30 (ORCPT ); Mon, 7 Sep 2015 12:29:26 -0400 Received: from mail-pa0-f49.google.com ([209.85.220.49]:32940 "EHLO mail-pa0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751336AbbIGQ3Z (ORCPT ); Mon, 7 Sep 2015 12:29:25 -0400 Received: by pacex6 with SMTP id ex6so100533204pac.0; Mon, 07 Sep 2015 09:29:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:date:message-id:in-reply-to:references:subject; bh=xSRicPce56qcVrJyv7+kee/uNfPAMz37n2b9MnNWtzo=; b=tXi3uotUkQwI9RLiZ5AeqCTSu+UDoYeOsAssLm6buPLUYvZ8jFSNoESsc37PvCcNDb bbWO3gpnwlhbcBSe4gMngZTeU3cjINomMZmZ0Tght5yuxu6IIs4pabUNBRdADDn5AFvX RqlARnhDvYvp8yETcH8CM+9t28Qd7bNwqywZY57YMMRirQOHurZcMHW/e7xSKxFHQqAg CUkLgfk+3l9/pRkIJuVWxWFUEw9QuctItKIBOjYkbrEqd96XmrsPlpzHFrkp50txrI+z E25IMdrGM7qJBPx1Eb7lc5c6JIDHgqy8n7lm+WBzp8RiNSdWbpcQiFCHhoBKNcWocrz+ nw+g== X-Received: by 10.68.233.134 with SMTP id tw6mr48509630pbc.22.1441643365441; Mon, 07 Sep 2015 09:29:25 -0700 (PDT) Received: from [127.0.0.1] (s214090.ppp.asahi-net.or.jp. [220.157.214.90]) by smtp.gmail.com with ESMTPSA id y9sm328116pdp.17.2015.09.07.09.29.21 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 07 Sep 2015 09:29:23 -0700 (PDT) From: Magnus Damm To: linux-clk@vger.kernel.org Cc: kuninori.morimoto.gx@renesas.com, linux-sh@vger.kernel.org, mturquette@baylibre.com, gaku.inami.xw@bp.renesas.com, sboyd@codeaurora.org, horms@verge.net.au, geert@linux-m68k.org, laurent.pinchart@ideasonboard.com, Magnus Damm Date: Tue, 08 Sep 2015 01:33:46 +0900 Message-Id: <20150907163346.475.69916.sendpatchset@little-apple> In-Reply-To: <20150907163252.475.18281.sendpatchset@little-apple> References: <20150907163252.475.18281.sendpatchset@little-apple> Subject: [PATCH v7 05/05] clk: shmobile: rcar-gen3: Add CPG/MSTP Clock Domain support Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Geert Uytterhoeven Add Clock Domain support to the R-Car Gen3 Clock Pulse Generator (CPG) driver using the generic PM Domain. This allows to power-manage the module clocks of SoC devices that are part of the CPG/MSTP Clock Domain using Runtime PM, or for system suspend/resume. SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed through an MSTP clock should be tagged in DT with a proper "power-domains" property. Signed-off-by: Geert Uytterhoeven Signed-off-by: Magnus Damm --- Changes since V6: - None Changes since V5: - Rebased to fit on top of updated CPG DT binding document Changes since V4: - Rebased to fit on top of updated CPG DT binding document Changes since V3: - Fixed so correct file is actually used. =) - Took V2 from Geert but filtered out Kconfig.platforms bits Documentation/devicetree/bindings/clock/renesas,rcar-gen3-cpg-clocks.txt | 26 +++++++++- drivers/clk/shmobile/clk-rcar-gen3.c | 2 2 files changed, 26 insertions(+), 2 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html --- 0009/Documentation/devicetree/bindings/clock/renesas,rcar-gen3-cpg-clocks.txt +++ work/Documentation/devicetree/bindings/clock/renesas,rcar-gen3-cpg-clocks.txt 2015-09-02 14:41:32.942366518 +0900 @@ -2,6 +2,8 @@ The CPG generates core clocks for the R-Car Gen3 SoCs. It includes three PLLs and several fixed ratio dividers. +The CPG also provides a Clock Domain for SoC devices, in combination with the +CPG Module Stop (MSTP) Clocks. Required Properties: @@ -14,9 +16,17 @@ Required Properties: - clocks: References to the parent clocks: first to the EXTAL clock - #clock-cells: Must be 1 - clock-indices: Indices of the exported clocks + - #power-domain-cells: Must be 0 -Example -------- +SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed +through an MSTP clock should refer to the CPG device node in their +"power-domains" property, as documented by the generic PM domain bindings in +Documentation/devicetree/bindings/power/power_domain.txt. + +Examples +-------- + + - CPG device node: cpg_clocks: cpg_clocks@e6150000 { compatible = "renesas,r8a7795-cpg-clocks", @@ -29,4 +39,16 @@ Example R8A7795_CLK_PLL1 R8A7795_CLK_PLL2 R8A7795_CLK_PLL3 R8A7795_CLK_PLL4 >; + #power-domain-cells = <0>; + }; + + - CPG/MSTP Clock Domain member device node: + + scif2: serial@e6e88000 { + compatible = "renesas,scif-r8a7795", "renesas,scif"; + reg = <0 0xe6e88000 0 64>; + interrupts = ; + clocks = <&mstp3_clks RCAR_R8A7795_CLK_SCIF2>; + clock-names = "sci_ick"; + power-domains = <&cpg_clocks>; }; --- 0009/drivers/clk/shmobile/clk-rcar-gen3.c +++ work/drivers/clk/shmobile/clk-rcar-gen3.c 2015-09-02 14:39:35.912366518 +0900 @@ -236,6 +236,8 @@ static void __init rcar_gen3_cpg_clocks_ } of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data); + + cpg_mstp_add_clk_domain(np); } CLK_OF_DECLARE(rcar_gen3_cpg_clks, "renesas,rcar-gen3-cpg-clocks", rcar_gen3_cpg_clocks_init);