From patchwork Thu Sep 17 06:33:00 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Magnus Damm X-Patchwork-Id: 7202611 X-Patchwork-Delegate: horms@verge.net.au Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 0441D9F380 for ; Thu, 17 Sep 2015 06:33:09 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 07FD2208C9 for ; Thu, 17 Sep 2015 06:33:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 142C72081F for ; Thu, 17 Sep 2015 06:33:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753356AbbIQGdD (ORCPT ); Thu, 17 Sep 2015 02:33:03 -0400 Received: from mail-pa0-f41.google.com ([209.85.220.41]:35042 "EHLO mail-pa0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752696AbbIQGdD (ORCPT ); Thu, 17 Sep 2015 02:33:03 -0400 Received: by pacfv12 with SMTP id fv12so11756153pac.2; Wed, 16 Sep 2015 23:33:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:date:message-id:in-reply-to:references:subject; bh=jKDrHMwG4ZvwD0z2cZT3Ui40KN5RMr1HgbqRnbQQVlY=; b=m55SwyA9g5K5J3l+JgGcCo/Sg7i7+KwMkINzHhZgB8SHwgMUMicC6rE2dPZR4Lj9ci GY0P2/6kmZf/Fg84VvPRZt9PR0uGGDqdKq2Adb520t2buzjmqCNCZ5lyM9/btt4BaRao xhp8qqO+/vxnUQLyZS8oCjAMTTOPNDksunJV4tXuHxwj2WEOQepKiHB6N9TGhLXb/xjM ld8XLIOe1DLgOR0TAuP20URt1ueJyjuH7xCcm0CNQxZFJNQd4BGOws6mWu35En4TJXY9 w90Z5YFMPvEyLn0h4tHwQk80H30T1m1lQTlQyX9uwQ/6osOs7+Mh703vwZXeo/XfWtaZ IFMw== X-Received: by 10.66.148.136 with SMTP id ts8mr70019657pab.15.1442471581583; Wed, 16 Sep 2015 23:33:01 -0700 (PDT) Received: from [127.0.0.1] (s214090.ppp.asahi-net.or.jp. [220.157.214.90]) by smtp.gmail.com with ESMTPSA id ql5sm1643943pac.46.2015.09.16.23.32.58 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 16 Sep 2015 23:33:00 -0700 (PDT) From: Magnus Damm To: linux-sh@vger.kernel.org Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, lorenzo.pieralisi@arm.com, keita.kobayashi.ym@renesas.com, horms@verge.net.au, geert@linux-m68k.org, laurent.pinchart@ideasonboard.com, Magnus Damm Date: Thu, 17 Sep 2015 15:33:00 +0900 Message-Id: <20150917063300.26016.23728.sendpatchset@little-apple> In-Reply-To: <20150917063240.26016.93772.sendpatchset@little-apple> References: <20150917063240.26016.93772.sendpatchset@little-apple> Subject: [PATCH v3 02/09] ARM: shmobile: Add APMU DT support via Enable method Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Magnus Damm Allow DT configuration of the APMU hardware in the case when the APMU is pointed out in the DTB via the enable-method. The ability to configure the APMU via C code is still kept intact to prevent DTB breakage for older SoCs that do not rely on the enable-method for SMP support. Signed-off-by: Magnus Damm --- Changes since V2: - Moved is_allowed declaration, break when allowed - thanks Geert! Changes since V1: - Adjusted to use .cpu_can_disable instead of .cpu_disable arch/arm/mach-shmobile/platsmp-apmu.c | 92 +++++++++++++++++++++++++++++++-- 1 file changed, 88 insertions(+), 4 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html --- 0001/arch/arm/mach-shmobile/platsmp-apmu.c +++ work/arch/arm/mach-shmobile/platsmp-apmu.c 2015-09-16 20:46:23.400513000 +0900 @@ -24,6 +24,7 @@ #include #include "common.h" #include "platsmp-apmu.h" +#include "rcar-gen2.h" static struct { void __iomem *iomem; @@ -117,15 +118,67 @@ static void apmu_parse_cfg(void (*fn)(st } } -void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus, - struct rcar_apmu_config *apmu_config, - int num) +static const struct of_device_id apmu_ids[] = { + { .compatible = "renesas,apmu" }, + { /*sentinel*/ } +}; + +static void apmu_parse_dt(void (*fn)(struct resource *res, int cpu, int bit)) +{ + struct device_node *np_apmu, *np_cpu; + struct resource res; + u32 id; + int bit, index; + + for_each_matching_node(np_apmu, apmu_ids) { + /* only enable the cluster that includes the boot CPU */ + bool is_allowed = false; + for (bit = 0; bit < CONFIG_NR_CPUS; bit++) { + np_cpu = of_parse_phandle(np_apmu, "cpus", bit); + if (np_cpu) { + if (!of_property_read_u32(np_cpu, "reg", &id)) { + if (id == cpu_logical_map(0)) { + is_allowed = true; + of_node_put(np_cpu); + break; + } + + } + of_node_put(np_cpu); + } + } + if (!is_allowed) + continue; + + for (bit = 0; bit < CONFIG_NR_CPUS; bit++) { + np_cpu = of_parse_phandle(np_apmu, "cpus", bit); + if (np_cpu) { + if (!of_property_read_u32(np_cpu, "reg", &id)) { + index = get_logical_index(id); + if ((index >= 0) && + !of_address_to_resource(np_apmu, + 0, &res)) + fn(&res, index, bit); + } + of_node_put(np_cpu); + } + } + of_node_put(np_apmu); + } +} + +static void __init shmobile_smp_apmu_setup_boot(void) { /* install boot code shared by all CPUs */ shmobile_boot_fn = virt_to_phys(shmobile_smp_boot); shmobile_boot_arg = MPIDR_HWID_BITMASK; +} - /* perform per-cpu setup */ +void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus, + struct rcar_apmu_config *apmu_config, + int num) +{ + shmobile_smp_apmu_setup_boot(); apmu_parse_cfg(apmu_init_cpu, apmu_config, num); } @@ -236,3 +289,34 @@ void __init shmobile_smp_apmu_suspend_in shmobile_suspend_ops.enter = shmobile_smp_apmu_enter_suspend; } #endif + +static void __init shmobile_smp_apmu_prepare_cpus_dt(unsigned int max_cpus) +{ + shmobile_smp_apmu_setup_boot(); + apmu_parse_dt(apmu_init_cpu); + rcar_gen2_pm_init(); +} + +static int shmobile_smp_apmu_boot_secondary_md21(unsigned int cpu, + struct task_struct *idle) +{ + /* Error out when hardware debug mode is enabled */ + if (rcar_gen2_read_mode_pins() & BIT(21)) { + pr_warn("Unable to boot CPU%u when MD21 is set\n", cpu); + return -ENOTSUPP; + } + + return shmobile_smp_apmu_boot_secondary(cpu, idle); +} + +static struct smp_operations apmu_smp_ops __initdata = { + .smp_prepare_cpus = shmobile_smp_apmu_prepare_cpus_dt, + .smp_boot_secondary = shmobile_smp_apmu_boot_secondary_md21, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_can_disable = shmobile_smp_cpu_can_disable, + .cpu_die = shmobile_smp_apmu_cpu_die, + .cpu_kill = shmobile_smp_apmu_cpu_kill, +#endif +}; + +CPU_METHOD_OF_DECLARE(shmobile_smp_apmu, "renesas,apmu", &apmu_smp_ops);