From patchwork Thu Oct 1 14:37:38 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Magnus Damm X-Patchwork-Id: 7309221 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id D156EBEEA4 for ; Thu, 1 Oct 2015 14:37:30 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6B98A20697 for ; Thu, 1 Oct 2015 14:37:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B5A0E20620 for ; Thu, 1 Oct 2015 14:37:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753120AbbJAOh0 (ORCPT ); Thu, 1 Oct 2015 10:37:26 -0400 Received: from mail-pa0-f41.google.com ([209.85.220.41]:33468 "EHLO mail-pa0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753109AbbJAOhX (ORCPT ); Thu, 1 Oct 2015 10:37:23 -0400 Received: by pacex6 with SMTP id ex6so76623007pac.0; Thu, 01 Oct 2015 07:37:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:date:message-id:in-reply-to:references:subject; bh=mPsVxe0KCDTQ6PCwOl0TwaeousMdFH5Xa+mbtscagZY=; b=ViQDe75n0PhJa03rhFoOKT6+S7E2wN7W3sRWMToQH5DuK6VsGdF48nKMYxx55tzwMN q2TfS5H+lbJPcn4WB7F3bmNhSejiI8rXjb11FvlGieBb3dmDxnkSlTQ0/Kyi6jv/4jYS 2SNLnCWmWGQ2q412b+b0eFYVGWAsxmeVnOqVr6xlN7nfYDnm2KrAoeEL8i11FOZ/vSKG b0F542coxXot4JkIiAcyZuiGwGvoRVS/953FhNwv/h49j9xBlNekdJEuKSWt8+gfJAJp 0j11PZe6I2+xORiNHDAgBE2bnAd18Y9eTIOlheCrU93RA13SZ2pAxKk4chT1e72Ilhz+ N/NQ== X-Received: by 10.66.144.199 with SMTP id so7mr12705754pab.42.1443710243067; Thu, 01 Oct 2015 07:37:23 -0700 (PDT) Received: from [127.0.0.1] (s214090.ppp.asahi-net.or.jp. [220.157.214.90]) by smtp.gmail.com with ESMTPSA id jo5sm7150121pbc.5.2015.10.01.07.37.19 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 01 Oct 2015 07:37:21 -0700 (PDT) From: Magnus Damm To: linux-clk@vger.kernel.org Cc: kuninori.morimoto.gx@renesas.com, gaku.inami.xw@bp.renesas.com, mturquette@baylibre.com, linux-sh@vger.kernel.org, sboyd@codeaurora.org, horms@verge.net.au, geert@linux-m68k.org, laurent.pinchart@ideasonboard.com, Magnus Damm Date: Thu, 01 Oct 2015 23:37:38 +0900 Message-Id: <20151001143738.20618.81835.sendpatchset@little-apple> In-Reply-To: <20151001143717.20618.26365.sendpatchset@little-apple> References: <20151001143717.20618.26365.sendpatchset@little-apple> Subject: [PATCH v8 02/05] clk: shmobile: Add Renesas R-Car Gen3 CPG support Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Magnus Damm This V8 patch adds initial CPG support for R-Car Generation 3 and in particular the R8A7795 SoC. The R-Car Gen3 clock hardware has a register write protection feature that needs to be shared between the CPG function and the MSTP hardware somehow. So far this feature is simply ignored. Signed-off-by: Gaku Inami Signed-off-by: Kuninori Morimoto Signed-off-by: Magnus Damm --- Changes since V7: (Magnus Damm ) - Removed clk-mstp.o from r8a7795 Makefile - Moved to earlier in the series Changes since V6: (Magnus Damm ) - Moved PLL1 div-by-2 unit to outside of the CPG - thanks Laurent! - Updated table to reflect PLL1 divider move. - Reworked clock registration loop to prevent re-registering clocks. Changes since V5: (Magnus Damm ) - Removed unused spinlock, use 0x3f as mask - thanks Laurent! - Fixed space -> tab for DT binding documentation - thanks Geert! - Postponed PLL1 divide-by-2 rewrite - requires a tad more effort. - Updated commit log Changes since V4: (Magnus Damm ) - Simplified clks array handling - thanks Geert! - Updated th DT binding documentation to reflect latest state - of_property_count_strings() -> of_property_count_u32_elems() fix Changes since V3: (Magnus Damm ) - Reworked driver to incorporate most feedback from Stephen Boyd - thanks!! - Major things like syscon and driver model require more discussion. - Added hunk to build drivers/clk/shmobile if ARCH_RENESAS is set. Changes since V2: (Magnus Damm ) - Reworked driver to rely on clock index instead of strings. - Dropped use of "clock-output-names". Earlier versions: Kuninori Morimoto Initial version: Gaku Inami Documentation/devicetree/bindings/clock/renesas,rcar-gen3-cpg-clocks.txt | 32 + drivers/clk/Makefile | 1 drivers/clk/shmobile/Makefile | 1 drivers/clk/shmobile/clk-rcar-gen3.c | 242 ++++++++++ 4 files changed, 276 insertions(+) -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html --- /dev/null +++ work/Documentation/devicetree/bindings/clock/renesas,rcar-gen3-cpg-clocks.txt 2015-10-01 18:42:49.020513000 +0900 @@ -0,0 +1,32 @@ +* Renesas R-Car Gen3 Clock Pulse Generator (CPG) + +The CPG generates core clocks for the R-Car Gen3 SoCs. It includes three PLLs +and several fixed ratio dividers. + +Required Properties: + + - compatible: Must be one of + - "renesas,r8a7795-cpg-clocks" for the r8a7795 CPG + - "renesas,rcar-gen3-cpg-clocks" for the generic R-Car Gen3 CPG + + - reg: Base address and length of the memory resource used by the CPG + + - clocks: References to the parent clocks: first to the EXTAL clock + - #clock-cells: Must be 1 + - clock-indices: Indices of the exported clocks + +Example +------- + + cpg_clocks: cpg_clocks@e6150000 { + compatible = "renesas,r8a7795-cpg-clocks", + "renesas,rcar-gen3-cpg-clocks"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>; + #clock-cells = <1>; + clock-indices = < + R8A7795_CLK_MAIN R8A7795_CLK_PLL0 + R8A7795_CLK_PLL1 R8A7795_CLK_PLL2 + R8A7795_CLK_PLL3 R8A7795_CLK_PLL4 + >; + }; --- 0001/drivers/clk/Makefile +++ work/drivers/clk/Makefile 2015-10-01 18:42:48.000513000 +0900 @@ -67,6 +67,7 @@ obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/ obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += shmobile/ +obj-$(CONFIG_ARCH_RENESAS) += shmobile/ obj-$(CONFIG_ARCH_SIRF) += sirf/ obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/ obj-$(CONFIG_PLAT_SPEAR) += spear/ --- 0002/drivers/clk/shmobile/Makefile +++ work/drivers/clk/shmobile/Makefile 2015-10-01 18:42:59.670513000 +0900 @@ -8,4 +8,5 @@ obj-$(CONFIG_ARCH_R8A7790) += clk-rcar- obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o clk-mstp.o clk-div6.o obj-$(CONFIG_ARCH_R8A7793) += clk-rcar-gen2.o clk-mstp.o clk-div6.o obj-$(CONFIG_ARCH_R8A7794) += clk-rcar-gen2.o clk-mstp.o clk-div6.o +obj-$(CONFIG_ARCH_R8A7795) += clk-rcar-gen3.o clk-div6.o obj-$(CONFIG_ARCH_SH73A0) += clk-sh73a0.o clk-mstp.o clk-div6.o --- /dev/null +++ work/drivers/clk/shmobile/clk-rcar-gen3.c 2015-10-01 18:42:49.020513000 +0900 @@ -0,0 +1,242 @@ +/* + * rcar_gen3 Core CPG Clocks + * + * Copyright (C) 2015 Renesas Electronics Corp. + * + * Based on rcar_gen2 Core CPG Clocks driver. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define RCAR_GEN3_CLK_MAIN 0 +#define RCAR_GEN3_CLK_PLL0 1 +#define RCAR_GEN3_CLK_PLL1 2 +#define RCAR_GEN3_CLK_PLL2 3 +#define RCAR_GEN3_CLK_PLL3 4 +#define RCAR_GEN3_CLK_PLL4 5 +#define RCAR_GEN3_CLK_NR 6 + +static const char * const rcar_gen3_clk_names[RCAR_GEN3_CLK_NR] = { + [RCAR_GEN3_CLK_MAIN] = "main", + [RCAR_GEN3_CLK_PLL0] = "pll0", + [RCAR_GEN3_CLK_PLL1] = "pll1", + [RCAR_GEN3_CLK_PLL2] = "pll2", + [RCAR_GEN3_CLK_PLL3] = "pll3", + [RCAR_GEN3_CLK_PLL4] = "pll4", +}; + +struct rcar_gen3_cpg { + struct clk_onecell_data data; + void __iomem *reg; + struct clk *clks[RCAR_GEN3_CLK_NR]; +}; + +#define CPG_PLL0CR 0x00d8 +#define CPG_PLL2CR 0x002c + +/* + * common function + */ +#define rcar_clk_readl(cpg, _reg) readl(cpg->reg + _reg) + +/* + * Reset register definitions. + */ +#define MODEMR 0xe6160060 + +static u32 rcar_gen3_read_mode_pins(void) +{ + static u32 mode; + static bool mode_valid; + + if (!mode_valid) { + void __iomem *modemr = ioremap_nocache(MODEMR, 4); + + BUG_ON(!modemr); + mode = ioread32(modemr); + iounmap(modemr); + mode_valid = true; + } + + return mode; +} + +/* ----------------------------------------------------------------------------- + * CPG Clock Data + */ + +/* + * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 + * 14 13 19 17 (MHz) + *------------------------------------------------------------------- + * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 + * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 + * 0 0 1 0 Prohibited setting + * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 + * 0 1 0 0 20 x 1 x150 x156 x120 x156 x120 + * 0 1 0 1 20 x 1 x150 x156 x120 x106 x120 + * 0 1 1 0 Prohibited setting + * 0 1 1 1 20 x 1 x150 x156 x120 x156 x120 + * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 + * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 + * 1 0 1 0 Prohibited setting + * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 + * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 + * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 + * 1 1 1 0 Prohibited setting + * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 + */ +#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ + (((md) & BIT(13)) >> 11) | \ + (((md) & BIT(19)) >> 18) | \ + (((md) & BIT(17)) >> 17)) +struct cpg_pll_config { + unsigned int extal_div; + unsigned int pll1_mult; + unsigned int pll3_mult; + unsigned int pll4_mult; +}; + +static const struct cpg_pll_config cpg_pll_configs[16] __initconst = { +/* EXTAL div PLL1 PLL3 PLL4 */ + { 1, 192, 192, 144, }, + { 1, 192, 128, 144, }, + { 0, 0, 0, 0, }, /* Prohibited setting */ + { 1, 192, 192, 144, }, + { 1, 156, 156, 120, }, + { 1, 156, 106, 120, }, + { 0, 0, 0, 0, }, /* Prohibited setting */ + { 1, 156, 156, 120, }, + { 1, 128, 128, 96, }, + { 1, 128, 84, 96, }, + { 0, 0, 0, 0, }, /* Prohibited setting */ + { 1, 128, 128, 96, }, + { 2, 192, 192, 144, }, + { 2, 192, 128, 144, }, + { 0, 0, 0, 0, }, /* Prohibited setting */ + { 2, 192, 192, 144, }, +}; + +/* ----------------------------------------------------------------------------- + * Initialization + */ + +static struct clk * __init +rcar_gen3_cpg_register_clk(struct device_node *np, struct rcar_gen3_cpg *cpg, + const struct cpg_pll_config *config, + unsigned int gen3_clk) +{ + const char *parent_name = rcar_gen3_clk_names[RCAR_GEN3_CLK_MAIN]; + unsigned int mult = 1; + unsigned int div = 1; + u32 value; + + switch (gen3_clk) { + case RCAR_GEN3_CLK_MAIN: + parent_name = of_clk_get_parent_name(np, 0); + div = config->extal_div; + break; + case RCAR_GEN3_CLK_PLL0: + /* PLL0 is a configurable multiplier clock. Register it as a + * fixed factor clock for now as there's no generic multiplier + * clock implementation and we currently have no need to change + * the multiplier value. + */ + value = rcar_clk_readl(cpg, CPG_PLL0CR); + mult = ((value >> 24) & 0x3f) + 1; + break; + case RCAR_GEN3_CLK_PLL1: + mult = config->pll1_mult; + break; + case RCAR_GEN3_CLK_PLL2: + /* PLL2 is a configurable multiplier clock. Register it as a + * fixed factor clock for now as there's no generic multiplier + * clock implementation and we currently have no need to change + * the multiplier value. + */ + value = rcar_clk_readl(cpg, CPG_PLL2CR); + mult = ((value >> 24) & 0x3f) + 1; + break; + case RCAR_GEN3_CLK_PLL3: + mult = config->pll3_mult; + break; + case RCAR_GEN3_CLK_PLL4: + mult = config->pll4_mult; + break; + default: + return ERR_PTR(-EINVAL); + } + + return clk_register_fixed_factor(NULL, rcar_gen3_clk_names[gen3_clk], + parent_name, 0, mult, div); +} + +static void __init rcar_gen3_cpg_clocks_init(struct device_node *np) +{ + const struct cpg_pll_config *config; + struct rcar_gen3_cpg *cpg; + u32 cpg_mode; + unsigned int i; + + cpg = kzalloc(sizeof(*cpg), GFP_KERNEL); + if (!cpg) + return; + + cpg->reg = of_iomap(np, 0); + if (WARN_ON(cpg->reg == NULL)) + return; + + cpg_mode = rcar_gen3_read_mode_pins(); + + config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; + if (!config->extal_div) { + pr_err("%s: Prohibited setting (cpg_mode=0x%x)\n", + __func__, cpg_mode); + return; + } + + for (i = 0; i < RCAR_GEN3_CLK_NR; ++i) + cpg->clks[i] = ERR_PTR(-ENOENT); + + for (i = 0; i < RCAR_GEN3_CLK_NR; ++i) { + struct clk *clk; + u32 idx; + int ret; + + ret = of_property_read_u32_index(np, "clock-indices", i, &idx); + if (ret < 0) + break; + + if (idx >= RCAR_GEN3_CLK_NR) { + pr_err("%s: skipping unsupported %u\n", __func__, idx); + } else if (cpg->clks[idx] != ERR_PTR(-ENOENT)) { + pr_err("%s: skipping already registered %u\n", + __func__, idx); + } else { + clk = rcar_gen3_cpg_register_clk(np, cpg, config, idx); + + if (IS_ERR(clk)) + pr_err("%s: unable to register %u (%ld)\n", + __func__, idx, PTR_ERR(clk)); + else + cpg->clks[idx] = clk; + } + } + + cpg->data.clks = cpg->clks; + cpg->data.clk_num = i; + + of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data); +} +CLK_OF_DECLARE(rcar_gen3_cpg_clks, "renesas,rcar-gen3-cpg-clocks", + rcar_gen3_cpg_clocks_init);