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[220.157.214.90]) by smtp.gmail.com with ESMTPSA id bh4sm12189374pbb.17.2015.11.05.23.52.20 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 05 Nov 2015 23:52:22 -0800 (PST) From: Magnus Damm To: linux-arm-kernel@lists.infradead.org Cc: linux@arm.linux.org.uk, geert+renesas@glider.be, linux-sh@vger.kernel.org, catalin.marinas@arm.com, Chris.Brandt@renesas.com, ezequiel@vanguardiasur.com.ar, u.kleine-koenig@pengutronix.de, Magnus Damm Date: Fri, 06 Nov 2015 16:53:19 +0900 Message-Id: <20151106075319.19378.64286.sendpatchset@little-apple> Subject: [PATCH] ARM: proc-v7: Put stack in data section, handle XIP case Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Magnus Damm Adjust the ARM v7 setup code to put the temporary stack in the data section and also use PLAT_PHYS_OFFSET to handle the XIP case. The common case of XIP=n the code is considered to be position independent while for XIP=y PLAT_PHYS_OFFSET is fixed. This is based on that early code in head.S invoking PROCINFO_INITFUNC seems position independent. At this point two places in proc-v7.S make use of the temporary stack so the PLAT_PHYS_OFFSET calculation is duplicated. The XIP=n case has been tested with CPU Hotplug on r8a7779 (Cortex A9 Quad) and Chris [CCed] has tested the XIP=y case. Signed-off-by: Magnus Damm Tested-by: Chris.Brandt@renesas.com --- Please let me know if considering XIP=y position independent is overkill, or if it is better to share code somehow. arch/arm/mm/proc-v7.S | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html --- 0001/arch/arm/mm/proc-v7.S +++ work/arch/arm/mm/proc-v7.S 2015-11-06 16:32:13.370513000 +0900 @@ -274,7 +274,15 @@ __v7_ca15mp_setup: __v7_b15mp_setup: __v7_ca17mp_setup: mov r10, #0 -1: adr r12, __v7_setup_stack @ the local stack +1: adr r11, __v7_setup_stack_ptr @ pointer to local stack + ldmia r11, {r0, r12} +#ifdef CONFIG_XIP_KERNEL + ldr r11, =PLAT_PHYS_OFFSET @ fixed address +#else + sub r11, r11, r0 @ position independent offset +#endif + add r12, r12, r11 @ phys address + sub r12, #PAGE_OFFSET stmia r12, {r0-r5, lr} @ v7_invalidate_l1 touches r0-r6 bl v7_invalidate_l1 ldmia r12, {r0-r5, lr} @@ -415,7 +423,15 @@ __v7_pj4b_setup: #endif /* CONFIG_CPU_PJ4B */ __v7_setup: - adr r12, __v7_setup_stack @ the local stack + adr r11, __v7_setup_stack_ptr @ pointer to local stack + ldmia r11, {r0, r12} +#ifdef CONFIG_XIP_KERNEL + ldr r11, =PLAT_PHYS_OFFSET @ fixed address +#else + sub r11, r11, r0 @ position independent offset +#endif + add r12, r12, r11 @ phys address + sub r12, #PAGE_OFFSET stmia r12, {r0-r5, lr} @ v7_invalidate_l1 touches r0-r6 bl v7_invalidate_l1 ldmia r12, {r0-r5, lr} @@ -482,6 +498,11 @@ __errata_finish: ret lr @ return to head.S:__ret ENDPROC(__v7_setup) +__v7_setup_stack_ptr: + .long . + .long __v7_setup_stack + + .data .align 2 __v7_setup_stack: .space 4 * 7 @ 12 registers