From patchwork Tue Apr 26 01:22:52 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rich Felker X-Patchwork-Id: 8933901 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id C13D1BF29F for ; Tue, 26 Apr 2016 01:22:58 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BC43C20122 for ; Tue, 26 Apr 2016 01:22:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DD9FA2011D for ; Tue, 26 Apr 2016 01:22:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751870AbcDZBW4 (ORCPT ); Mon, 25 Apr 2016 21:22:56 -0400 Received: from 216-12-86-13.cv.mvl.ntelos.net ([216.12.86.13]:57670 "EHLO brightrain.aerifal.cx" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750843AbcDZBW4 (ORCPT ); Mon, 25 Apr 2016 21:22:56 -0400 Received: from dalias by brightrain.aerifal.cx with local (Exim 3.15 #2) id 1auriG-00011A-00; Tue, 26 Apr 2016 01:22:52 +0000 Date: Mon, 25 Apr 2016 21:22:52 -0400 From: Rich Felker To: linux-sh@vger.kernel.org Cc: Yoshinori Sato Subject: [PATCH] sh: disable aliased page logic on NOMMU models Message-ID: <20160426012252.GA3892@brightrain.aerifal.cx> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP SH3/4 (with MMU) have a virtually indexed cache, requiring explicit work to avoid consistency problems arising from having the same physical address range cached in multiple cache lines. This is unneeded for the NOMMU case, and some of the resulting code paths (kmap_coherent) don't work. SH2 only avoided this problem by having a 4-way associative cache with way size equal to the page size (4k), yielding no cache index bits outside of the page offset and thus no aliases. Signed-off-by: Rich Felker --- See also the linux-sh thread "Fixing SH cache assumptions" from March 2016. I plan to include this patch as part of the patch series for J2 support now, and in the next (4.7) merge window. If/when there are SH models (J4?) with PIPT cache we can revisit extending the code to handle that case, but for now just handling nommu suffices. arch/sh/kernel/cpu/init.c | 4 ++++ arch/sh/mm/cache.c | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/arch/sh/kernel/cpu/init.c b/arch/sh/kernel/cpu/init.c index 0d7360d..bfd9e27 100644 --- a/arch/sh/kernel/cpu/init.c +++ b/arch/sh/kernel/cpu/init.c @@ -323,9 +323,13 @@ asmlinkage void cpu_init(void) cache_init(); if (raw_smp_processor_id() == 0) { +#ifdef CONFIG_MMU shm_align_mask = max_t(unsigned long, current_cpu_data.dcache.way_size - 1, PAGE_SIZE - 1); +#else + shm_align_mask = PAGE_SIZE - 1; +#endif /* Boot CPU sets the cache shape */ detect_cache_shape(); diff --git a/arch/sh/mm/cache.c b/arch/sh/mm/cache.c index e58cfbf..776d664 100644 --- a/arch/sh/mm/cache.c +++ b/arch/sh/mm/cache.c @@ -244,7 +244,11 @@ void flush_cache_sigtramp(unsigned long address) static void compute_alias(struct cache_info *c) { +#ifdef CONFIG_MMU c->alias_mask = ((c->sets - 1) << c->entry_shift) & ~(PAGE_SIZE - 1); +#else + c->alias_mask = 0; +#endif c->n_aliases = c->alias_mask ? (c->alias_mask >> PAGE_SHIFT) + 1 : 0; }