From patchwork Mon Mar 26 21:25:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Petazzoni X-Patchwork-Id: 10308755 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 869E860212 for ; Mon, 26 Mar 2018 21:25:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7BB022890C for ; Mon, 26 Mar 2018 21:25:52 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6E193298A4; Mon, 26 Mar 2018 21:25:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DA36A2890C for ; Mon, 26 Mar 2018 21:25:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752653AbeCZVZu (ORCPT ); Mon, 26 Mar 2018 17:25:50 -0400 Received: from mail.bootlin.com ([62.4.15.54]:56049 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752221AbeCZVZt (ORCPT ); Mon, 26 Mar 2018 17:25:49 -0400 Received: by mail.bootlin.com (Postfix, from userid 110) id B6E09208C1; Mon, 26 Mar 2018 23:25:47 +0200 (CEST) Received: from localhost (LFbn-TOU-1-408-85.w86-206.abo.wanadoo.fr [86.206.234.85]) by mail.bootlin.com (Postfix) with ESMTPSA id 215C020877; Mon, 26 Mar 2018 23:25:32 +0200 (CEST) From: Thomas Petazzoni To: Yoshinori Sato , Rich Felker , linux-sh@vger.kernel.org Cc: Thomas Petazzoni Subject: [PATCH 1/5] drivers/sh/clk: add support for CLK_SET_TO_ENABLE flag Date: Mon, 26 Mar 2018 23:25:23 +0200 Message-Id: <20180326212527.12565-2-thomas.petazzoni@bootlin.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180326212527.12565-1-thomas.petazzoni@bootlin.com> References: <20180326212527.12565-1-thomas.petazzoni@bootlin.com> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The current sh_clk_mstp_{enable,disable} functions assume that enable_bit must be cleared to enable the clock, and set to disable the clock. However, this clock type is used for the PHY of the SH7786 PCIe controller, which has the opposite polarity: set to enable, clear to disable. In order to properly support this clock, we introduce a CLK_SET_TO_ENABLE flag. Signed-off-by: Thomas Petazzoni --- drivers/sh/clk/cpg.c | 10 ++++++++-- include/linux/sh_clk.h | 2 ++ 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/sh/clk/cpg.c b/drivers/sh/clk/cpg.c index 7442bc130055..ecb1ab9a8f1d 100644 --- a/drivers/sh/clk/cpg.c +++ b/drivers/sh/clk/cpg.c @@ -53,7 +53,10 @@ static unsigned int r32(const void __iomem *addr) static int sh_clk_mstp_enable(struct clk *clk) { - sh_clk_write(sh_clk_read(clk) & ~(1 << clk->enable_bit), clk); + if (clk->flags & CLK_SET_TO_ENABLE) + sh_clk_write(sh_clk_read(clk) | (1 << clk->enable_bit), clk); + else + sh_clk_write(sh_clk_read(clk) & ~(1 << clk->enable_bit), clk); if (clk->status_reg) { unsigned int (*read)(const void __iomem *addr); int i; @@ -82,7 +85,10 @@ static int sh_clk_mstp_enable(struct clk *clk) static void sh_clk_mstp_disable(struct clk *clk) { - sh_clk_write(sh_clk_read(clk) | (1 << clk->enable_bit), clk); + if (clk->flags & CLK_SET_TO_ENABLE) + sh_clk_write(sh_clk_read(clk) & ~(1 << clk->enable_bit), clk); + else + sh_clk_write(sh_clk_read(clk) | (1 << clk->enable_bit), clk); } static struct sh_clk_ops sh_clk_mstp_clk_ops = { diff --git a/include/linux/sh_clk.h b/include/linux/sh_clk.h index 7bed5be886c6..0413570a7141 100644 --- a/include/linux/sh_clk.h +++ b/include/linux/sh_clk.h @@ -73,6 +73,8 @@ struct clk { #define CLK_MASK_DIV_ON_DISABLE BIT(4) +#define CLK_SET_TO_ENABLE BIT(5) + #define CLK_ENABLE_REG_MASK (CLK_ENABLE_REG_32BIT | \ CLK_ENABLE_REG_16BIT | \ CLK_ENABLE_REG_8BIT)