From patchwork Mon Mar 26 21:25:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Petazzoni X-Patchwork-Id: 10308767 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D49E960212 for ; Mon, 26 Mar 2018 21:26:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CB4162890C for ; Mon, 26 Mar 2018 21:26:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C01A8298AB; Mon, 26 Mar 2018 21:26:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 097E32890C for ; Mon, 26 Mar 2018 21:26:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752532AbeCZVZ7 (ORCPT ); Mon, 26 Mar 2018 17:25:59 -0400 Received: from mail.bootlin.com ([62.4.15.54]:56071 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751730AbeCZVZz (ORCPT ); Mon, 26 Mar 2018 17:25:55 -0400 Received: by mail.bootlin.com (Postfix, from userid 110) id 9F8B72087E; Mon, 26 Mar 2018 23:25:53 +0200 (CEST) Received: from localhost (LFbn-TOU-1-408-85.w86-206.abo.wanadoo.fr [86.206.234.85]) by mail.bootlin.com (Postfix) with ESMTPSA id BB4EE20893; Mon, 26 Mar 2018 23:25:32 +0200 (CEST) From: Thomas Petazzoni To: Yoshinori Sato , Rich Felker , linux-sh@vger.kernel.org Cc: Thomas Petazzoni Subject: [PATCH 3/5] arch/sh: pcie-sh7786: properly wait for PHY operations ACK Date: Mon, 26 Mar 2018 23:25:25 +0200 Message-Id: <20180326212527.12565-4-thomas.petazzoni@bootlin.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180326212527.12565-1-thomas.petazzoni@bootlin.com> References: <20180326212527.12565-1-thomas.petazzoni@bootlin.com> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP When doing a PHY write, the following sequence must be done: - Write the PCIEPHYDOUTR and PCIEPHYADDR registers - Wait for the ACK bit to be set - Clear the PCIEPHYDOUTR and PCIEPHYADDR registers - Wait for the ACK bit to clear However, in the last step, the current code waits for the ACK bit to be set, which is not correct, and does not match the SH7786 datasheet. This commit fixes that by improving the phy_wait_for_ack() to indicate whether we want to wait for the ACK bit to be set or cleared, and then use this new argument in phy_write_reg(). Signed-off-by: Thomas Petazzoni --- arch/sh/drivers/pci/pcie-sh7786.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c index 29df5c6fe22c..01a45ce8b2da 100644 --- a/arch/sh/drivers/pci/pcie-sh7786.c +++ b/arch/sh/drivers/pci/pcie-sh7786.c @@ -152,12 +152,17 @@ static void sh7786_pci_fixup(struct pci_dev *dev) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_SH7786, sh7786_pci_fixup); -static int __init phy_wait_for_ack(struct pci_channel *chan) +static int phy_wait_for_ack(struct pci_channel *chan, bool set) { unsigned int timeout = 100; while (timeout--) { - if (pci_read_reg(chan, SH4A_PCIEPHYADRR) & (1 << BITS_ACK)) + int state = + pci_read_reg(chan, SH4A_PCIEPHYADRR) & (1 << BITS_ACK); + if (set && state) + return 0; + + if (!set && !state) return 0; udelay(100); @@ -192,13 +197,13 @@ static void __init phy_write_reg(struct pci_channel *chan, unsigned int addr, pci_write_reg(chan, data, SH4A_PCIEPHYDOUTR); pci_write_reg(chan, phyaddr, SH4A_PCIEPHYADRR); - phy_wait_for_ack(chan); + phy_wait_for_ack(chan, true); /* Clear command */ pci_write_reg(chan, 0, SH4A_PCIEPHYDOUTR); pci_write_reg(chan, 0, SH4A_PCIEPHYADRR); - phy_wait_for_ack(chan); + phy_wait_for_ack(chan, false); } static int __init pcie_clk_init(struct sh7786_pcie_port *port)