diff mbox series

[09/15] pinctrl: sh-pfc: sh7734: Remove bogus IPSR10 value

Message ID 20181213182714.26094-10-geert+renesas@glider.be (mailing list archive)
State New, archived
Headers show
Series pinctrl: sh-pfc: Fix config register descriptions | expand

Commit Message

Geert Uytterhoeven Dec. 13, 2018, 6:27 p.m. UTC 
The IP10[5:3] field in Peripheral Function Select Register 10 has a
width of 3 bits, i.e. it allows programming one out of 8 different
configurations.
However, 9 values are provided instead of 8, overflowing into the
subsequent field in the register, and thus breaking the configuration of
the latter.

Fix this by dropping a bogus zero value.

Fixes: ac1ebc2190f575fc ("sh-pfc: Add sh7734 pinmux support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 drivers/pinctrl/sh-pfc/pfc-sh7734.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Simon Horman Dec. 17, 2018, 2:31 p.m. UTC | #1 
On Thu, Dec 13, 2018 at 07:27:08PM +0100, Geert Uytterhoeven wrote:
> The IP10[5:3] field in Peripheral Function Select Register 10 has a
> width of 3 bits, i.e. it allows programming one out of 8 different
> configurations.
> However, 9 values are provided instead of 8, overflowing into the
> subsequent field in the register, and thus breaking the configuration of
> the latter.
> 
> Fix this by dropping a bogus zero value.
> 
> Fixes: ac1ebc2190f575fc ("sh-pfc: Add sh7734 pinmux support")
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
diff mbox series

Patch

diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7734.c b/drivers/pinctrl/sh-pfc/pfc-sh7734.c
index 04062f642d3e62de..cad70f9cf5699f0c 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7734.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7734.c
@@ -2228,7 +2228,7 @@  static const struct pinmux_cfg_reg pinmux_config_regs[] = {
 		FN_LCD_CL1_B, 0, 0, 0,
 	    /* IP10_5_3 [3] */
 		FN_SSI_WS23, FN_VI1_5_B, FN_TX1_D, FN_HSCK0_C, FN_FALE_B,
-		FN_LCD_DON_B, 0, 0, 0,
+		FN_LCD_DON_B, 0, 0,
 	    /* IP10_2_0 [3] */
 		FN_SSI_SCK23, FN_VI1_4_B, FN_RX1_D, FN_FCLE_B,
 		FN_LCD_DATA15_B, 0, 0, 0 }