| Message ID | 20200626080717.1999041-10-hch@lst.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [01/10] sh: remove -Werror from Makefiles | expand |
On 6/26/20 3:07 AM, Christoph Hellwig wrote: > The code handling non-coherent DMA depends on being able to remap code > as non-cached. But that can't be done without an MMU, so using this > option on NOMMU builds is broken. I'm working on a nommu j-core board that's doing DMA behind the OS's back at the moment, which I have a todo item to teach the kernel about. The DMA does not go through the cache, there's currently a cache flush before looking at the result instead. How should this be wired up after your patch? Rob
On Sat, Jun 27, 2020 at 08:01:17PM -0500, Rob Landley wrote: > On 6/26/20 3:07 AM, Christoph Hellwig wrote: > > The code handling non-coherent DMA depends on being able to remap code > > as non-cached. But that can't be done without an MMU, so using this > > option on NOMMU builds is broken. > > I'm working on a nommu j-core board that's doing DMA behind the OS's back at the > moment, which I have a todo item to teach the kernel about. The DMA does not go > through the cache, there's currently a cache flush before looking at the result > instead. > > How should this be wired up after your patch? The problem with nommu and non-coherent dma is the dma_alloc_coherent calls. Most platforms with an mmu set a nocache bit through the page tables (including sh), but that option obviously doesn't exist for nommu. Some hardware has an uncached window where access is uncached automatically if access through specific kernel virtual addresses, for that the architecture needs to impement the arch_dma_set_uncached helper and select CONFIG_ARCH_HAS_DMA_SET_UNCACHED. If that also doesn't exist you'll need some sort of pool of always uncached memory (set by the firmware or early startup code). That currently doesn't exist in generic code, but we have a bunch of architectures implementing that in arch_dma_alloc. I plan to have a common implementation of the pool soon hopefully. Streaming DMA just works if you reuse the existing arch_sync_dma_for_device implementation.
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index f8027eee08edae..337eb496c45a0a 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -61,6 +61,7 @@ config SUPERH select MAY_HAVE_SPARSE_IRQ select MODULES_USE_ELF_RELA select NEED_SG_DMA_LENGTH + select NO_DMA if !MMU && !DMA_COHERENT select NO_GENERIC_PCI_IOPORT_MAP if PCI select OLD_SIGACTION select OLD_SIGSUSPEND @@ -135,7 +136,7 @@ config DMA_COHERENT bool config DMA_NONCOHERENT - def_bool !DMA_COHERENT + def_bool !NO_DMA && !DMA_COHERENT select ARCH_HAS_SYNC_DMA_FOR_DEVICE config PGTABLE_LEVELS
The code handling non-coherent DMA depends on being able to remap code as non-cached. But that can't be done without an MMU, so using this option on NOMMU builds is broken. Signed-off-by: Christoph Hellwig <hch@lst.de> --- arch/sh/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)