From patchwork Thu Aug 27 13:57:26 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 44263 Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n7RDvblj027718 for ; Thu, 27 Aug 2009 13:57:37 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752666AbZH0N5e (ORCPT ); Thu, 27 Aug 2009 09:57:34 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1752689AbZH0N5d (ORCPT ); Thu, 27 Aug 2009 09:57:33 -0400 Received: from mail.renesas.com ([202.234.163.13]:65242 "EHLO mail02.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752666AbZH0N5d (ORCPT ); Thu, 27 Aug 2009 09:57:33 -0400 X-AuditID: ac140385-0000000a000002de-6e-4a9690c53f7c Received: from guardian02.idc.renesas.com ([172.20.8.201]) by mail02.idc.renesas.com (sendmail) with ESMTP id n7RDvPh6019452; Thu, 27 Aug 2009 22:57:25 +0900 (JST) Received: (from root@localhost) by guardian02.idc.renesas.com with id n7RDvQIF001402; Thu, 27 Aug 2009 22:57:26 +0900 (JST) Received: from mta02.idc.renesas.com (localhost [127.0.0.1]) by mta02.idc.renesas.com with ESMTP id n7RDvRwf011309; Thu, 27 Aug 2009 22:57:27 +0900 (JST) Received: from [172.30.8.157] by ims05.idc.renesas.com (Sendmail) with ESMTPA id <0KP100AZ2G3QQU@ims05.idc.renesas.com>; Thu, 27 Aug 2009 22:57:26 +0900 (JST) Date: Thu, 27 Aug 2009 22:57:26 +0900 From: Yoshihiro Shimoda Subject: Re: [BUG] arch/sh/include/mach-common/mach/sh7785lcr.h: PCA9564_ADDR is 29bit-only In-reply-to: <20090827041504.GC696@linux-sh.org> To: Paul Mundt Cc: yoshii.takashi@renesas.com, Ra?l Porcel , SH-Linux Message-id: <4A9690C6.3030300@renesas.com> MIME-version: 1.0 Content-type: text/plain; charset=ISO-8859-1 Content-transfer-encoding: 7bit User-Agent: Thunderbird 2.0.0.14 (Windows/20080421) References: <4A95800A.7020603@gentoo.org> <20090827120103.a24e8837.yoshii.takashi@renesas.com> <20090827041504.GC696@linux-sh.org> X-Brightmail-Tracker: AAAAAA== Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org Paul Mundt wrote: > On Thu, Aug 27, 2009 at 12:01:03PM +0900, yoshii.takashi@renesas.com wrote: >> Oh, sorry. >> This might be because the board I sent you was a special version. >> You (and possibly others who use this version) should revert that commit. >> I'm really sorry for inconvenient. >> >> Paul, are there any good way to support this kind of small differences? >> Is it ok to add configuration menu item like below? >> > Presumably we can figure the version out from the FPGA? If so, we can > just figure out which devices to register, and have different devices for > different versions. > > If we can't figure it out from the FPGA, then the next best bet is to use > the mach types, the version information can be encoded in a new > mach-type, and we can simply have a mach_is_xxx() check for determining > the board version and doing the appropriate fixups. We already do this > today for some boards (highlander, r2d, etc.). Thank you very much for your comment. Unfortunately, this board don't have version register in FPGA. So I made a patch that it adds mach_is_sh7785lcr_pt(). Would you check this patch? Thanks, Yoshihiro Shimoda --- Subject: [PATCH] sh: sh7785lcr: fix prototype board on 32bit MMU mode. Fix the problem that cannot work PCA9564 on 32bit MMU mode using prototype board. Signed-off-by: Yoshihiro Shimoda --- arch/sh/boards/Kconfig | 7 +++++++ arch/sh/boards/board-sh7785lcr.c | 18 ++++++++++++++++++ arch/sh/include/mach-common/mach/sh7785lcr.h | 2 ++ arch/sh/tools/mach-types | 1 + 4 files changed, 28 insertions(+), 0 deletions(-) diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig index b66f6d1..ee5bb20 100644 --- a/arch/sh/boards/Kconfig +++ b/arch/sh/boards/Kconfig @@ -171,6 +171,13 @@ config SH_SH7785LCR_29BIT_PHYSMAPS DIP switch(S2-5). If you set the DIP switch for S2-5 = ON, you can access all on-board device in 29bit address mode. +config SH_SH7785LCR_PT + bool "SH7785LCR prototype board on 32-bit MMU mode" + depends on SH_SH7785LCR && 32BIT + default n + help + If you use prototype board, this option is enabled. + config SH_URQUELL bool "Urquell" depends on CPU_SUBTYPE_SH7786 diff --git a/arch/sh/boards/board-sh7785lcr.c b/arch/sh/boards/board-sh7785lcr.c index 42410a1..726427c 100644 --- a/arch/sh/boards/board-sh7785lcr.c +++ b/arch/sh/boards/board-sh7785lcr.c @@ -223,6 +223,19 @@ static struct platform_device sm501_device = { .resource = sm501_resources, }; +static struct resource i2c_proto_resources[] = { + [0] = { + .start = PCA9564_PROTO_32BIT_ADDR, + .end = PCA9564_PROTO_32BIT_ADDR + PCA9564_SIZE - 1, + .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT, + }, + [1] = { + .start = 12, + .end = 12, + .flags = IORESOURCE_IRQ, + }, +}; + static struct resource i2c_resources[] = { [0] = { .start = PCA9564_ADDR, @@ -271,6 +284,11 @@ static int __init sh7785lcr_devices_setup(void) i2c_register_board_info(0, sh7785lcr_i2c_devices, ARRAY_SIZE(sh7785lcr_i2c_devices)); + if (mach_is_sh7785lcr_pt()) { + i2c_device.resource = &i2c_proto_resources; + i2c_device.num_resources = ARRAY_SIZE(i2c_proto_resources); + } + return platform_add_devices(sh7785lcr_devices, ARRAY_SIZE(sh7785lcr_devices)); } diff --git a/arch/sh/include/mach-common/mach/sh7785lcr.h b/arch/sh/include/mach-common/mach/sh7785lcr.h index 90011d4..1292ae5 100644 --- a/arch/sh/include/mach-common/mach/sh7785lcr.h +++ b/arch/sh/include/mach-common/mach/sh7785lcr.h @@ -35,6 +35,8 @@ #define PCA9564_ADDR 0x06000000 /* I2C */ #define PCA9564_SIZE 0x00000100 +#define PCA9564_PROTO_32BIT_ADDR 0x14000000 + #define SM107_MEM_ADDR 0x10000000 #define SM107_MEM_SIZE 0x00e00000 #define SM107_REG_ADDR 0x13e00000 diff --git a/arch/sh/tools/mach-types b/arch/sh/tools/mach-types index b573628..6639b25 100644 --- a/arch/sh/tools/mach-types +++ b/arch/sh/tools/mach-types @@ -53,6 +53,7 @@ RSK7203 SH_RSK7203 AP325RXA SH_AP325RXA SH7763RDP SH_SH7763RDP SH7785LCR SH_SH7785LCR +SH7785LCR_PT SH_SH7785LCR_PT URQUELL SH_URQUELL ESPT SH_ESPT POLARIS SH_POLARIS