From patchwork Fri Sep 26 02:39:53 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Khiem Nguyen X-Patchwork-Id: 4978131 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 5B8609F3DF for ; Fri, 26 Sep 2014 02:39:57 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8BEB220274 for ; Fri, 26 Sep 2014 02:39:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A1B4220265 for ; Fri, 26 Sep 2014 02:39:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752570AbaIZCjz (ORCPT ); Thu, 25 Sep 2014 22:39:55 -0400 Received: from relmlor2.renesas.com ([210.160.252.172]:63410 "EHLO relmlie1.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752386AbaIZCjy (ORCPT ); Thu, 25 Sep 2014 22:39:54 -0400 Received: from unknown (HELO relmlir2.idc.renesas.com) ([10.200.68.152]) by relmlie1.idc.renesas.com with ESMTP; 26 Sep 2014 11:39:53 +0900 Received: from relmlac3.idc.renesas.com (relmlac3.idc.renesas.com [10.200.69.23]) by relmlir2.idc.renesas.com (Postfix) with ESMTP id 6F0744C3E3; Fri, 26 Sep 2014 11:39:53 +0900 (JST) Received: by relmlac3.idc.renesas.com (Postfix, from userid 0) id 5AC7F180A1; Fri, 26 Sep 2014 11:39:53 +0900 (JST) Received: from relmlac3.idc.renesas.com (localhost [127.0.0.1]) by relmlac3.idc.renesas.com (Postfix) with ESMTP id 550C3180A0; Fri, 26 Sep 2014 11:39:53 +0900 (JST) Received: from relmlii1.idc.renesas.com [10.200.68.65] by relmlac3.idc.renesas.com with ESMTP id MAU02734; Fri, 26 Sep 2014 11:39:53 +0900 X-IronPort-AV: E=Sophos;i="5.04,601,1406559600"; d="scan'208";a="169968176" Received: from hqdg0130.wireless.renesas.com (HELO [10.161.20.130]) ([10.161.20.130]) by relmlii1.idc.renesas.com with ESMTP; 26 Sep 2014 11:39:53 +0900 Message-ID: <5424D1F9.1090006@renesas.com> Date: Fri, 26 Sep 2014 11:39:53 +0900 From: Khiem Nguyen User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:31.0) Gecko/20100101 Thunderbird/31.1.2 MIME-Version: 1.0 To: Magnus Damm , Simon Horman CC: khiem.nguyen.xt@renesas.com, Linux-sh list , KEITA KOBAYASHI Subject: [PATCH RFC 1/7] ARM: shmobile: use common ARMv7 cache disabling code Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The effort to consolidate ARMv7 cache disabling code via macro v7_exit_coherency_flush() was introduced by 'commit 39792c7cf311 ("ARM: 7861/1: cacheflush: consolidate single-CPU ARMv7 cache disabling code")'. The code was made use in core powerdown and cluster powerdown in other SoC. Hence, it's worth changing our code to use it. Signed-off-by: Khiem Nguyen --- arch/arm/mach-shmobile/platsmp-apmu.c | 27 +-------------------------- 1 file changed, 1 insertion(+), 26 deletions(-) diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c b/arch/arm/mach-shmobile/platsmp-apmu.c index 3bfb1a0..21f8ddd 100644 --- a/arch/arm/mach-shmobile/platsmp-apmu.c +++ b/arch/arm/mach-shmobile/platsmp-apmu.c @@ -152,34 +152,9 @@ int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle) #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_SUSPEND) || \ defined(CONFIG_CPU_IDLE) -/* nicked from arch/arm/mach-exynos/hotplug.c */ static inline void cpu_enter_lowpower_a15(void) { - unsigned int v; - - asm volatile( - " mrc p15, 0, %0, c1, c0, 0\n" - " bic %0, %0, %1\n" - " mcr p15, 0, %0, c1, c0, 0\n" - : "=&r" (v) - : "Ir" (CR_C) - : "cc"); - - flush_cache_louis(); - - asm volatile( - /* - * Turn off coherency - */ - " mrc p15, 0, %0, c1, c0, 1\n" - " bic %0, %0, %1\n" - " mcr p15, 0, %0, c1, c0, 1\n" - : "=&r" (v) - : "Ir" (0x40) - : "cc"); - - isb(); - dsb(); + v7_exit_coherency_flush(louis); } void shmobile_smp_apmu_cpu_shutdown(unsigned int cpu)