From patchwork Sat Jan 17 00:58:40 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 5651161 X-Patchwork-Delegate: horms@verge.net.au Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id BED90C058D for ; Sat, 17 Jan 2015 00:59:05 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DDE092040F for ; Sat, 17 Jan 2015 00:59:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D9824203AC for ; Sat, 17 Jan 2015 00:59:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751678AbbAQA7D (ORCPT ); Fri, 16 Jan 2015 19:59:03 -0500 Received: from kirsty.vergenet.net ([202.4.237.240]:57610 "EHLO kirsty.vergenet.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752096AbbAQA7D (ORCPT ); Fri, 16 Jan 2015 19:59:03 -0500 Received: from penelope.kanocho.kobe.vergenet.net (g1-27-253-251-6.bmobile.ne.jp [27.253.251.6]) by kirsty.vergenet.net (Postfix) with ESMTP id AFF6F26719A; Sat, 17 Jan 2015 11:58:56 +1100 (EST) Received: by penelope.kanocho.kobe.vergenet.net (Postfix, from userid 7100) id 7BABC60AC0; Sat, 17 Jan 2015 09:58:46 +0900 (JST) From: Simon Horman To: linux-sh@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Magnus Damm , Geert Uytterhoeven , Simon Horman Subject: [PATCH 07/11] ARM: shmobile: Add DT bindings for Renesas memory controllers Date: Sat, 17 Jan 2015 09:58:40 +0900 Message-Id: <753b9c9cfdfeae57f956c55e1ccdfcf2d90e6196.1421380713.git.horms+renesas@verge.net.au> X-Mailer: git-send-email 2.1.4 In-Reply-To: References: Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Geert Uytterhoeven Add DT bindings for Renesas R-Mobile and SH-Mobile memory controllers. Currently memory controller device nodes are used only to reference PM domains, and prevent these PM domains from being powered down, which would crash the system. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- .../renesas-memory-controllers.txt | 44 ++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/renesas-memory-controllers.txt diff --git a/Documentation/devicetree/bindings/memory-controllers/renesas-memory-controllers.txt b/Documentation/devicetree/bindings/memory-controllers/renesas-memory-controllers.txt new file mode 100644 index 0000000..c64b792 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/renesas-memory-controllers.txt @@ -0,0 +1,44 @@ +DT bindings for Renesas R-Mobile and SH-Mobile memory controllers +================================================================= + +Renesas R-Mobile and SH-Mobile SoCs contain one or more memory controllers. +These memory controllers differ from one SoC variant to another, and are called +by different names ("DDR Bus Controller (DBSC)", "DDR3 Bus State Controller +(DBSC3)", "SDRAM Bus State Controller (SBSC)"). + +Currently memory controller device nodes are used only to reference PM +domains, and prevent these PM domains from being powered down, which would +crash the system. + +As there exist no actual drivers for these controllers yet, these bindings +should be considered EXPERIMENTAL for now. + +Required properties: + - compatible: Must be one of the following SoC-specific values: + - "renesas,dbsc-r8a73a4" (R-Mobile APE6) + - "renesas,dbsc3-r8a7740" (R-Mobile A1) + - "renesas,sbsc-sh73a0" (SH-Mobile AG5) + - reg: Must contain the base address and length of the memory controller's + registers. + +Optional properties: + - interrupts: Must contain a list of interrupt specifiers for memory + controller interrupts, if available. + - interrupts-names: Must contain a list of interrupt names corresponding to + the interrupts in the interrupts property, if available. + Valid interrupt names are: + - "sec" (secure interrupt) + - "temp" (normal (temperature) interrupt) + - power-domains: Must contain a reference to the PM domain that the memory + controller belongs to, if available. + +Example: + + sbsc1: memory-controller@fe400000 { + compatible = "renesas,sbsc-sh73a0"; + reg = <0xfe400000 0x400>; + interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>, + <0 36 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "sec", "temp"; + power-domains = <&pd_a4bc0>; + };