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[202.32.14.49]) by mx.google.com with ESMTPSA id am2sm11718070pbc.59.2014.07.21.22.34.49 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 21 Jul 2014 22:34:50 -0700 (PDT) Date: Mon, 21 Jul 2014 22:34:50 -0700 (PDT) Message-ID: <874myahs7b.wl%kuninori.morimoto.gx@renesas.com> To: Simon , Ian Molton , Chris Ball Cc: TOSHIAKI KOMATSU , NAOYA SHIIBA , Magnus , Linux-SH , (Renesas) goda , linux-mmc@vger.kernel.org, ryo.kataoka.wt@renesas.com, shinobu.uehara.xc@renesas.com, kouei.abe.cp@renesas.com In-Reply-To: <87egxehsec.wl%kuninori.morimoto.gx@gmail.com> References: <87simtenpi.wl%kuninori.morimoto.gx@renesas.com> <87pphxe2q0.wl%kuninori.morimoto.gx@renesas.com> <53AD638C.5060907@renesas.com> <87egxehsec.wl%kuninori.morimoto.gx@gmail.com> From: Kuninori Morimoto Subject: [PATCH 07/10] mmc: tmio: check ILL_FUNC instead of CBSY User-Agent: Wanderlust/2.14.0 Emacs/23.3 Mule/6.0 MIME-Version: 1.0 (generated by SEMI 1.14.6 - "Maruoka") Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Shinobu Uehara Some controllers need to check SD bus status when writing data. Then, it checks ILL_FUNC bit on SD_INFO2 register, and this method is controlled via TMIO_MMC_HAS_IDLE_WAIT flags. Same method is required on tmio_mmc_data_irq() which will be called after writing data. Current driver is checking CBSY bit for this purpose, but, some controllers doesn't have CBSY bit. This patch checks ILL_FUNC bit instead of CBSY bit if it has TMIO_MMC_HAS_IDLE_WAIT flags [Kuninori Morimoto: tidyuped for upstreaming] Signed-off-by: Shinobu Uehara Signed-off-by: Kuninori Morimoto --- drivers/mmc/host/tmio_mmc_pio.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/tmio_mmc_pio.c b/drivers/mmc/host/tmio_mmc_pio.c index e51a993..b19d0cd 100644 --- a/drivers/mmc/host/tmio_mmc_pio.c +++ b/drivers/mmc/host/tmio_mmc_pio.c @@ -475,6 +475,9 @@ static void tmio_mmc_data_irq(struct tmio_mmc_host *host) goto out; if (host->chan_tx && (data->flags & MMC_DATA_WRITE) && !host->force_pio) { + u32 status = sd_ctrl_read32(host, CTL_STATUS); + bool done = false; + /* * Has all data been written out yet? Testing on SuperH showed, * that in most cases the first interrupt comes already with the @@ -483,7 +486,15 @@ static void tmio_mmc_data_irq(struct tmio_mmc_host *host) * DATAEND interrupt with the BUSY bit set, in this cases * waiting for one more interrupt fixes the problem. */ - if (!(sd_ctrl_read32(host, CTL_STATUS) & TMIO_STAT_CMD_BUSY)) { + if (host->pdata->flags & TMIO_MMC_HAS_IDLE_WAIT) { + if (status & TMIO_STAT_ILL_FUNC) + done = true; + } else { + if (!(status & TMIO_STAT_CMD_BUSY)) + done = true; + } + + if (done) { tmio_mmc_disable_mmc_irqs(host, TMIO_STAT_DATAEND); tasklet_schedule(&host->dma_complete); }