From patchwork Wed May 13 02:18:22 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kuninori Morimoto X-Patchwork-Id: 6393301 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E0BF7BEEE1 for ; Wed, 13 May 2015 02:18:30 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CB263203EB for ; Wed, 13 May 2015 02:18:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AF1A020390 for ; Wed, 13 May 2015 02:18:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965035AbbEMCS2 (ORCPT ); Tue, 12 May 2015 22:18:28 -0400 Received: from relmlor2.renesas.com ([210.160.252.172]:62721 "EHLO relmlie1.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S965002AbbEMCS1 (ORCPT ); Tue, 12 May 2015 22:18:27 -0400 Received: from unknown (HELO relmlir1.idc.renesas.com) ([10.200.68.151]) by relmlie1.idc.renesas.com with ESMTP; 13 May 2015 11:18:26 +0900 Received: from relmlac1.idc.renesas.com (relmlac1.idc.renesas.com [10.200.69.21]) by relmlir1.idc.renesas.com (Postfix) with ESMTP id 3746E51DE9; Wed, 13 May 2015 11:18:26 +0900 (JST) Received: by relmlac1.idc.renesas.com (Postfix, from userid 0) id 2EDC98002E; Wed, 13 May 2015 11:18:26 +0900 (JST) Received: from relmlac1.idc.renesas.com (localhost [127.0.0.1]) by relmlac1.idc.renesas.com (Postfix) with ESMTP id 01D138002D; Wed, 13 May 2015 11:18:26 +0900 (JST) Received: from relmlii2.idc.renesas.com [10.200.68.66] by relmlac1.idc.renesas.com with ESMTP id MAF12026; Wed, 13 May 2015 11:18:25 +0900 X-IronPort-AV: E=Sophos;i="5.13,418,1427727600"; d="scan'208";a="187239319" Received: from mail-sg1lp0094.outbound.protection.outlook.com (HELO APAC01-SG1-obe.outbound.protection.outlook.com) ([207.46.51.94]) by relmlii2.idc.renesas.com with ESMTP/TLS/AES256-SHA; 13 May 2015 11:18:24 +0900 Authentication-Results: linaro.org; dkim=none (message not signed) header.d=none; Received: from morimoto-PC.renesas.com (211.11.155.132) by SINPR06MB315.apcprd06.prod.outlook.com (10.141.115.153) with Microsoft SMTP Server (TLS) id 15.1.160.19; Wed, 13 May 2015 02:18:22 +0000 Message-ID: <87617xfchj.wl%kuninori.morimoto.gx@renesas.com> From: Kuninori Morimoto Subject: [PATCH 3/3 v5] mmc: sh_mmcif: calculate best clock with parent clock User-Agent: Wanderlust/2.15.9 Emacs/24.3 Mule/6.0 MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") To: Ulf Hansson CC: linux-mmc , Simon , Magnus , Linux-SH , Laurent , Geert Uytterhoeven , kobayashi In-Reply-To: <87a8x9fck7.wl%kuninori.morimoto.gx@renesas.com> References: <873840a4ch.wl%kuninori.morimoto.gx@renesas.com> <87a8x9fck7.wl%kuninori.morimoto.gx@renesas.com> Date: Wed, 13 May 2015 02:18:22 +0000 X-Originating-IP: [211.11.155.132] X-ClientProxiedBy: KAWPR01CA0033.jpnprd01.prod.outlook.com (25.165.48.143) To SINPR06MB315.apcprd06.prod.outlook.com (10.141.115.153) X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:SINPR06MB315; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(5005006)(3002001); SRVR:SINPR06MB315; BCL:0; PCL:0; RULEID:; SRVR:SINPR06MB315; X-Forefront-PRVS: 0575F81B58 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10019020)(6009001)(122386002)(2950100001)(77156002)(62966003)(50466002)(77096005)(40100003)(23726002)(4001350100001)(36756003)(107886002)(83506001)(5001960100002)(110136002)(19580395003)(19580405001)(92566002)(189998001)(76176999)(50986999)(54356999)(87976001)(229853001)(86362001)(42186005)(46102003)(53416004)(33646002)(66066001)(47776003)(46406003)(4001430100001); DIR:OUT; SFP:1102; SCL:1; SRVR:SINPR06MB315; H:morimoto-PC.renesas.com; FPR:; SPF:None; MLV:sfv; LANG:en; X-OriginatorOrg: renesas.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 May 2015 02:18:22.1010 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: SINPR06MB315 Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Kuninori Morimoto MMCIF IP on R-Car series has parent clock which can be set several rate, and it was not implemented on old SH-Mobile series (= SH-Mobile series parent clock was fixed rate) R-Car series MMCIF can use more high speed access if it setup parent clock. This patch adds parent clock setup method, and r8a7790/r8a7791 can use it. Signed-off-by: Kuninori Morimoto Tested-by: Keita Kobayashi --- v4 -> v5 - get clock data from compatible drivers/mmc/host/sh_mmcif.c | 92 ++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 83 insertions(+), 9 deletions(-) diff --git a/drivers/mmc/host/sh_mmcif.c b/drivers/mmc/host/sh_mmcif.c index e13c5f41..7ade263 100644 --- a/drivers/mmc/host/sh_mmcif.c +++ b/drivers/mmc/host/sh_mmcif.c @@ -57,6 +57,7 @@ #include #include #include +#include #include #include #include @@ -224,6 +225,15 @@ enum sh_mmcif_wait_for { MMCIF_WAIT_FOR_STOP, }; +/* + * difference for each SoC + */ +struct sh_mmcif_ver { + u32 clkdiv_map; /* see CE_CLK_CTRL::CLKDIV */ + unsigned int pf_min; /* parent frequency min */ + unsigned int pf_max; /* parent frequency max */ +}; + struct sh_mmcif_host { struct mmc_host *mmc; struct mmc_request *mrq; @@ -248,6 +258,7 @@ struct sh_mmcif_host { bool ccs_enable; /* Command Completion Signal support */ bool clk_ctrl2_enable; struct mutex thread_lock; + const struct sh_mmcif_ver *ver; /* DMA support */ struct dma_chan *chan_rx; @@ -256,8 +267,16 @@ struct sh_mmcif_host { bool dma_active; }; +static const struct sh_mmcif_ver sh_mmcif_gen2 = { + .clkdiv_map = 0x3ff, + .pf_min = 12187500, + .pf_max = 97500000, +}; + static const struct of_device_id sh_mmcif_of_match[] = { { .compatible = "renesas,sh-mmcif" }, + { .compatible = "renesas,mmcif-r8a7790", .data = &sh_mmcif_gen2 }, + { .compatible = "renesas,mmcif-r8a7791", .data = &sh_mmcif_gen2 }, { } }; MODULE_DEVICE_TABLE(of, sh_mmcif_of_match); @@ -492,19 +511,56 @@ static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) struct sh_mmcif_plat_data *p = dev->platform_data; bool sup_pclk = p ? p->sup_pclk : false; unsigned int current_clk = clk_get_rate(host->clk); + unsigned int clkdiv; sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR); if (!clk) return; - if (sup_pclk && clk == current_clk) - sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK); - else - sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & - ((fls(DIV_ROUND_UP(current_clk, - clk) - 1) - 1) << 16)); + if (host->ver) { + const struct sh_mmcif_ver *ver = host->ver; + unsigned int freq, best_freq, myclk, div, diff_min, diff; + int i; + + clkdiv = 0; + diff_min = ~0; + best_freq = 0; + for (i = 31; i >= 0; i--) { + if (!((1 << i) & ver->clkdiv_map)) + continue; + + /* + * clk = parent_freq / div + * -> parent_freq = clk x div + */ + + div = 1 << (i + 1); + freq = clk_round_rate(host->clk, clk * div); + myclk = freq / div; + diff = (myclk > clk) ? myclk - clk : clk - myclk; + + if (diff <= diff_min) { + best_freq = freq; + clkdiv = i; + diff_min = diff; + } + } + + dev_dbg(dev, "clk %u/%u (%u, 0x%x)\n", + (best_freq / (1 << (clkdiv + 1))), clk, + best_freq, clkdiv); + + clk_set_rate(host->clk, best_freq); + clkdiv = clkdiv << 16; + } else if (sup_pclk && clk == current_clk) { + clkdiv = CLK_SUP_PCLK; + } else { + clkdiv = (fls(DIV_ROUND_UP(current_clk, clk) - 1) - 1) << 16; + } + + sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & clkdiv); sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); } @@ -1000,10 +1056,28 @@ static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq) static void sh_mmcif_clk_setup(struct sh_mmcif_host *host) { - unsigned int clk = clk_get_rate(host->clk); + struct device *dev = sh_mmcif_host_to_dev(host); + const struct of_device_id *of_id; + const struct sh_mmcif_ver *ver = NULL; + + of_id = of_match_device(sh_mmcif_of_match, dev); + if (of_id) + ver = of_id->data; + + if (ver) { + host->mmc->f_min = ver->pf_min / (1 << fls(ver->clkdiv_map)); + host->mmc->f_max = ver->pf_max / (1 << ffs(ver->clkdiv_map)); + + host->ver = ver; + } else { + unsigned int clk = clk_get_rate(host->clk); + + host->mmc->f_max = clk / 2; + host->mmc->f_min = clk / 512; + } - host->mmc->f_max = clk / 2; - host->mmc->f_min = clk / 512; + dev_dbg(dev, "clk max/min = %d/%d\n", + host->mmc->f_max, host->mmc->f_min); } static void sh_mmcif_set_power(struct sh_mmcif_host *host, struct mmc_ios *ios)