From patchwork Wed Oct 2 08:33:36 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kuninori Morimoto X-Patchwork-Id: 2973431 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 3881ABFF0B for ; Wed, 2 Oct 2013 08:33:41 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id EFB5D20399 for ; Wed, 2 Oct 2013 08:33:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CAF4720397 for ; Wed, 2 Oct 2013 08:33:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753051Ab3JBIdi (ORCPT ); Wed, 2 Oct 2013 04:33:38 -0400 Received: from mail-pb0-f52.google.com ([209.85.160.52]:58397 "EHLO mail-pb0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752921Ab3JBIdh (ORCPT ); Wed, 2 Oct 2013 04:33:37 -0400 Received: by mail-pb0-f52.google.com with SMTP id wz12so572503pbc.11 for ; Wed, 02 Oct 2013 01:33:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=date:sender:message-id:to:cc:in-reply-to:references:from:subject :mime-version:content-type; bh=OHbKZH8/RVAm1w18lGt4ZZbaimmMyUKUdbjMPcorjCg=; b=oHlR+cMOQth7D3HZKkMBxcYGIKdoqGFBgebkGQkaacgfhlml2iT4aLGpVN9mfe1EhI GldJrddEfsGslgRx1EtXZZKQ6WIveDVp5dirX7GMEyFN+VFlTiOiEVo4j2WvKcuUdlAe 1Li0tbnisoZlsr47i37Zu298T9Klg3iSN3/PR7wMTnaSzn6SmsakR0ZP2x26leNO1LiC 4QVC/hBYTH8fto8T9pOQoxGirQ66MBVAuQtEuLHKe75cs0Z2g4hCz0QkF71R9ldYyoQk jd7kpmcAL4LGouq0t8DDDrzDS7uD87TpQu4JBDqkH/CIHdeKenzpIlwNuZuYqK4PB1Il Z67g== X-Received: by 10.68.231.71 with SMTP id te7mr77503pbc.203.1380702816903; Wed, 02 Oct 2013 01:33:36 -0700 (PDT) Received: from morimoto-Dell-XPS420.gmail.com ([202.32.14.49]) by mx.google.com with ESMTPSA id os4sm670654pbb.25.1969.12.31.16.00.00 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Wed, 02 Oct 2013 01:33:36 -0700 (PDT) Date: Wed, 02 Oct 2013 01:33:36 -0700 (PDT) Message-ID: <87eh84ysvj.wl%kuninori.morimoto.gx@renesas.com> To: Simon Cc: Magnus , linux-sh@vger.kernel.org, Kuninori Morimoto In-Reply-To: <87ioxgyszq.wl%kuninori.morimoto.gx@renesas.com> References: <87y56cyzdo.wl%kuninori.morimoto.gx@renesas.com> <87ioxgyszq.wl%kuninori.morimoto.gx@renesas.com> From: Kuninori Morimoto Subject: [PATCH 3/4 v2] ARM: shmobile: bockw: add SMSC support on reference MIME-Version: 1.0 (generated by SEMI 1.14.6 - "Maruoka") Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch enables INTC IRQ, and SMSC IRQ. Signed-off-by: Kuninori Morimoto --- v1 -> v2 - patch was splited, only -reference.c arch/arm/mach-shmobile/board-bockw-reference.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/mach-shmobile/board-bockw-reference.c b/arch/arm/mach-shmobile/board-bockw-reference.c index 1a7c893..ae88fda 100644 --- a/arch/arm/mach-shmobile/board-bockw-reference.c +++ b/arch/arm/mach-shmobile/board-bockw-reference.c @@ -36,15 +36,35 @@ static const struct pinctrl_map bockw_pinctrl_map[] = { "scif0_ctrl", "scif0"), }; +#define FPGA 0x18200000 +#define IRQ0MR 0x30 +#define COMCTLR 0x101c static void __init bockw_init(void) { + static void __iomem *fpga; + r8a7778_clock_init(); + r8a7778_init_irq_extpin_dt(1); pinctrl_register_mappings(bockw_pinctrl_map, ARRAY_SIZE(bockw_pinctrl_map)); r8a7778_pinmux_init(); r8a7778_add_dt_devices(); + fpga = ioremap_nocache(FPGA, SZ_1M); + if (fpga) { + /* + * CAUTION + * + * IRQ0/1 is cascaded interrupt from FPGA. + * it should be cared in the future + * Now, it is assuming IRQ0 was used only from SMSC. + */ + u16 val = ioread16(fpga + IRQ0MR); + val &= ~(1 << 4); /* enable SMSC911x */ + iowrite16(val, fpga + IRQ0MR); + } + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); }