diff mbox

[2/3] ARM: shmobile: r8a7791: add MSTP10 support on DTSI

Message ID 87lht2enz5.wl%kuninori.morimoto.gx@renesas.com (mailing list archive)
State Accepted
Commit ee9141522dcf13f861ed3cef6490c6cbfaafefb9
Headers show

Commit Message

Kuninori Morimoto June 12, 2014, 4:44 a.m. UTC 
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
---
 arch/arm/boot/dts/r8a7791.dtsi            |   33 +++++++++++++++++++++++++++++
 include/dt-bindings/clock/r8a7791-clock.h |   26 +++++++++++++++++++++++
 2 files changed, 59 insertions(+)

Comments

Geert Uytterhoeven June 12, 2014, 6:46 a.m. UTC | #1 
On Thu, Jun 12, 2014 at 6:44 AM, Kuninori Morimoto
<kuninori.morimoto.gx@renesas.com> wrote:
> From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>

Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

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when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
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Simon Horman June 13, 2014, 7:47 a.m. UTC | #2 
On Thu, Jun 12, 2014 at 08:46:45AM +0200, Geert Uytterhoeven wrote:
> On Thu, Jun 12, 2014 at 6:44 AM, Kuninori Morimoto
> <kuninori.morimoto.gx@renesas.com> wrote:
> > From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
> >
> > Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
> 
> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>

Thanks, I will queue this up.
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Sergei Shtylyov Jan. 28, 2016, 8:38 p.m. UTC | #3 
Hello.

On 06/12/2014 08:44 AM, Kuninori Morimoto wrote:

    Sorry for digging out the ancient patch...

> From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
> ---
>   arch/arm/boot/dts/r8a7791.dtsi            |   33 +++++++++++++++++++++++++++++
>   include/dt-bindings/clock/r8a7791-clock.h |   26 +++++++++++++++++++++++
>   2 files changed, 59 insertions(+)
>
> diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
> index f3b6219..380d058 100644
> --- a/arch/arm/boot/dts/r8a7791.dtsi
> +++ b/arch/arm/boot/dts/r8a7791.dtsi
> @@ -865,6 +865,39 @@
>   				"rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2",
>   				"i2c1", "i2c0";
>   		};
> +		mstp10_clks: mstp10_clks@e6150998 {
> +			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
> +			reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
> +			clocks = <&p_clk>,
> +				<&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
> +				<&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,

    But don't SSI[0-9] clocks all depend on SSI(all)? Shouldn't the above 10 
entries be
<&mstp10_clks R8A7791_CLK_SSI_ALL> like it was done to SCU(all)?

> +				<&p_clk>,
> +				<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
> +				<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
> +				<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
> +				<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
> +				<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
> +				<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>;

MBR, Sergei

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Kuninori Morimoto Feb. 8, 2016, 12:39 a.m. UTC | #4 
Hi Sergei

> > +		mstp10_clks: mstp10_clks@e6150998 {
> > +			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
> > +			reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
> > +			clocks = <&p_clk>,
> > +				<&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
> > +				<&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
> 
>    But don't SSI[0-9] clocks all depend on SSI(all)? Shouldn't the
> above 10 entries be
> <&mstp10_clks R8A7791_CLK_SSI_ALL> like it was done to SCU(all)?

Basically, you are correct.
I forgot detail, but SSI(all) will be enabled by normal pm_runtime_xxx().
And it had clock enable order dependency before.
(I think it was solved by using clock-indices feature)

It is not very correct indeed, but basically no problem I think.
But do you have some issues ?
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Sergei Shtylyov Feb. 8, 2016, 1:54 p.m. UTC | #5 
On 02/08/2016 03:39 AM, Kuninori Morimoto wrote:

>>> +		mstp10_clks: mstp10_clks@e6150998 {
>>> +			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
>>> +			reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
>>> +			clocks = <&p_clk>,
>>> +				<&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
>>> +				<&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
>>
>>     But don't SSI[0-9] clocks all depend on SSI(all)? Shouldn't the
>> above 10 entries be
>> <&mstp10_clks R8A7791_CLK_SSI_ALL> like it was done to SCU(all)?
>
> Basically, you are correct.
> I forgot detail, but SSI(all) will be enabled by normal pm_runtime_xxx().
> And it had clock enable order dependency before.
> (I think it was solved by using clock-indices feature)

    Not sure I understand.

> It is not very correct indeed, but basically no problem I think.
> But do you have some issues ?

    Just was looking at the manual writing the R8A7794 device tree audio 
support and this inconsistency came up.

MBR, Sergei

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diff mbox

Patch

diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index f3b6219..380d058 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -865,6 +865,39 @@ 
 				"rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2",
 				"i2c1", "i2c0";
 		};
+		mstp10_clks: mstp10_clks@e6150998 {
+			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
+			reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
+			clocks = <&p_clk>,
+				<&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
+				<&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
+				<&p_clk>,
+				<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
+				<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
+				<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
+				<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
+				<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
+				<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>;
+
+			#clock-cells = <1>;
+			clock-indices = <
+				R8A7791_CLK_SSI_ALL
+				R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5
+				R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0
+				R8A7791_CLK_SCU_ALL
+				R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0
+				R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5
+				R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0
+			>;
+			clock-output-names =
+				"ssi-all",
+				"ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
+				"ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
+				"scu-all",
+				"scu-dvc1", "scu-dvc0",
+				"scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
+				"scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
+		};
 		mstp11_clks: mstp11_clks@e615099c {
 			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 			reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h
index b050d18..0410bea 100644
--- a/include/dt-bindings/clock/r8a7791-clock.h
+++ b/include/dt-bindings/clock/r8a7791-clock.h
@@ -107,6 +107,32 @@ 
 #define R8A7791_CLK_I2C1		30
 #define R8A7791_CLK_I2C0		31
 
+/* MSTP10 */
+#define R8A7791_CLK_SSI_ALL		5
+#define R8A7791_CLK_SSI9		6
+#define R8A7791_CLK_SSI8		7
+#define R8A7791_CLK_SSI7		8
+#define R8A7791_CLK_SSI6		9
+#define R8A7791_CLK_SSI5		10
+#define R8A7791_CLK_SSI4		11
+#define R8A7791_CLK_SSI3		12
+#define R8A7791_CLK_SSI2		13
+#define R8A7791_CLK_SSI1		14
+#define R8A7791_CLK_SSI0		15
+#define R8A7791_CLK_SCU_ALL		17
+#define R8A7791_CLK_SCU_DVC1		18
+#define R8A7791_CLK_SCU_DVC0		19
+#define R8A7791_CLK_SCU_SRC9		22
+#define R8A7791_CLK_SCU_SRC8		23
+#define R8A7791_CLK_SCU_SRC7		24
+#define R8A7791_CLK_SCU_SRC6		25
+#define R8A7791_CLK_SCU_SRC5		26
+#define R8A7791_CLK_SCU_SRC4		27
+#define R8A7791_CLK_SCU_SRC3		28
+#define R8A7791_CLK_SCU_SRC2		29
+#define R8A7791_CLK_SCU_SRC1		30
+#define R8A7791_CLK_SCU_SRC0		31
+
 /* MSTP11 */
 #define R8A7791_CLK_SCIFA3		6
 #define R8A7791_CLK_SCIFA4		7