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[7/7] ARM: shmobile: porter: enable internal PCI and USB PHY

Message ID 99f7445ea41c0187cd2e78bcb58cdd9e6c1756e5.1444868963.git.horms+renesas@verge.net.au (mailing list archive)
State Accepted
Commit 99f7445ea41c0187cd2e78bcb58cdd9e6c1756e5
Headers show

Commit Message

Simon Horman Oct. 15, 2015, 12:34 a.m. UTC 
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

Enable  internal AHB-PCI bridges for the USB EHCI/OHCI controllers attached
to them and also enable  USB PHY device  for the Porter board.  We have to
enable  everything in one patch since EHCI/OHCI devices are already linked
to the USB PHY device.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/boot/dts/r8a7791-porter.dts | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)
diff mbox

Patch

diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts
index c46aad3954f4..fe0f12fc02a1 100644
--- a/arch/arm/boot/dts/r8a7791-porter.dts
+++ b/arch/arm/boot/dts/r8a7791-porter.dts
@@ -120,6 +120,16 @@ 
 		renesas,function = "i2c2";
 	};
 
+	usb0_pins: usb0 {
+		renesas,groups = "usb0";
+		renesas,function = "usb0";
+	};
+
+	usb1_pins: usb1 {
+		renesas,groups = "usb1";
+		renesas,function = "usb1";
+	};
+
 	vin0_pins: vin0 {
 		renesas,groups = "vin0_data8", "vin0_clk";
 		renesas,function = "vin0";
@@ -245,6 +255,24 @@ 
 	};
 };
 
+&pci0 {
+	pinctrl-0 = <&usb0_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&pci1 {
+	pinctrl-0 = <&usb1_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&usbphy {
+	status = "okay";
+};
+
 &pcie_bus_clk {
 	status = "okay";
 };